XCVU125-2FLVD1517I 鏅傞枔锛�2025/4/28 20:23:00 闁辫畝锛�35

XCVU125-2FLVD1517I 鏄竴娆剧敱 Xilinx锛堢従(xi脿n)鐐� AMD 鏃椾笅锛夌敓鐢�(ch菐n)鐨� UltraScale+ 绯诲垪 FPGA 鑺墖銆傝┎绯诲垪鑺墖鍩轰簬鍏堥€�(j矛n)鐨� FinFET 宸ヨ棟鎶€琛�(sh霉)锛屾彁渚涢珮鎬ц兘銆侀珮瀵嗗害閭忚集璩囨簮鍜屽挤(qi谩ng)澶х殑 DSP 鍔熻兘锛岄仼鐢ㄤ簬寰�(f霉)闆滅殑淇¤櫉铏曠悊銆侀€氫俊绯荤当(t菕ng)銆佹暩(sh霉)鎿�(j霉)涓績鍔犻€�銆佽埅绌鸿埅澶╁拰鍦嬮槻绛夋噳(y墨ng)鐢ㄩ牁(l菒ng)鍩熴€�
銆€銆€瑭插瀷铏熶腑鐨� XCVU 琛ㄧず鍏跺爆浜� Virtex UltraScale+ 绯诲垪锛岃€屽悗绾�(x霉)鐨勬暩(sh霉)瀛楀拰瀛楁瘝鍓囧畾缇╀簡鍏烽珨鐨勭敘(ch菐n)鍝侀厤缃�銆侀€熷害绛夌礆浠ュ強灏佽褰㈠紡銆傛鍨嬭櫉鏀寔澶氱ó楂橀€熸帴鍙ｅ崝(xi茅)璀�锛屽 PCIe Gen4銆丆CIX 鍜屼互澶恫(w菐ng) MAC锛屽悓鏅傚叿鍌欓潏娲荤殑鍙法绋嬭兘鍔�銆�

鍙冩暩(sh霉)

绯诲垪锛歏irtex UltraScale+
銆€銆€宸ヨ棟锛�16nm FinFET
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細绱� 125 钀€�
銆€銆€RAM 瀹归噺锛氱磩 80MB
銆€銆€DSP Slice 鏁�(sh霉)閲忥細6800
銆€銆€I/O 鏁�(sh霉)閲忥細鏈€澶� 1517 鍊�
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆€銆€渚涢浕闆诲锛氭牳蹇冮浕澹� 0.8V锛岃紨鍔╅浕澹� 1.8V/3.3V
銆€銆€灏佽椤炲瀷锛欶LGA (Fine Line Grid Array)
銆€銆€閫熷害绛夌礆锛�-2锛堣〃绀轰腑绛夋€ц兘鐗堟湰锛�

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1. 楂樺瘑搴﹂倧杓硣婧愶細XCVU125 鎻愪緵瓒呴亷 125 钀€嬮倧杓柈鍏冿紝鑳藉婊胯冻寰�(f霉)闆滆ō(sh猫)瑷堢殑闇€姹�銆�
銆€銆€2. 寮�(qi谩ng)澶х殑 DSP 鏀寔锛氬収(n猫i)缃� 6800 鍊� DSP Slice锛岄仼鍚堥珮鎬ц兘瑷堢畻浠诲嫏(w霉)锛屼緥濡傛烤娉㈠櫒瀵�(sh铆)鐝�(xi脿n)銆佺煩闄ｉ亱(y霉n)绠楀拰 FFT 铏曠悊銆�
銆€銆€3. 楂橀€熶覆琛屾敹鐧�(f膩)鍣細闆嗘垚澶氱祫楂橀仈(d谩) 32.75Gbps 鐨勬敹鐧�(f膩)鍣ㄦā濉婏紝鏀寔鍚勭ó閫氫俊鍗�(xi茅)璀�銆�
銆€銆€4. 澶у閲忓祵鍏ュ紡瀛樺劜锛氬収(n猫i)閮ㄥ寘鍚珮閬�(d谩) 80MB 鐨� Block RAM 鍜� UltraRAM锛屾笡灏戜簡灏嶅閮ㄥ瓨鍎茬殑闇€姹傘€�
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銆€銆€7. 瀹夊叏鍔熻兘锛氭敮鎸� AES 鍔犲瘑銆丼HA 绠楁硶绛夊绋畨鍏ㄦ(j墨)鍒�锛岀⒑淇濊ō(sh猫)瑷堢殑瀹夊叏鎬с€�

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