鏅傞枔锛�2025/4/28 10:51:05
闁辫畝锛�36
XCVU11P-1FSGD2104E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖銆傝┎绯诲垪鑺墖閲囩敤鑷虹⿳闆� 16nm FinFET Plus 宸ヨ棟鍒堕��锛屾彁渚涢珮鎬ц兘鍜岄珮瀵嗗害鐨勯倧杓硣婧�锛岄仼鍚堜簬鏁�(sh霉)鎿�(j霉)涓績鍔犻��銆佺恫(w菐ng)绲″姛鑳借櫅鎿寲 (NFV)銆侀珮绱氶椐涘摗杓斿姪绯荤当(t菕ng) (ADAS) 鍜屽叾浠栬▓绠楀瘑闆嗗瀷鎳夌敤銆�
銆�銆�閫欐 FPGA 閰嶅倷浜嗚睈瀵岀殑 DSP Slice 鍜� Block RAM 璩囨簮锛屽苟鏀寔澶氱ó楂橀�熶覆琛屾帴鍙�锛屽 PCIe Gen4 鍜岄珮閬� 32.75Gbps 鐨勬敹鐧�(f膩)鍣ㄩ�熺巼銆�
宸ヨ棟锛�16nm
銆�銆�閭忚集鍠厓锛氱磩 2,100,000
銆�銆�DSP Slice锛氱磩 8,820
銆�銆�Block RAM锛氱磩 6,840 Kb
銆�銆�鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲忥細96
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 32.75 Gbps
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 1,540
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster SPI銆丼lave SPI銆丅PI銆丣TAG
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�灏佽椤炲瀷锛欶SGD2104
XCVU11P-1FSGD2104E 鎻愪緵浜嗗挤澶х殑瑷堢畻鎬ц兘鑸囬潏娲绘�э紝鑳藉閬╂噳寤ｆ硾鐨勬噳鐢ㄩ渶姹�銆備富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樺閲忛倧杓硣婧愶細瓒呭ぇ瑕�(gu墨)妯＄殑閭忚集鍠厓鏁�(sh霉)閲忥紝閬╃敤浜庡京闆滅畻娉曞鐝�(xi脿n)鍜屾暩(sh霉)鎿�(j霉)铏曠悊浠诲嫏銆�
銆�銆�2. 楂橀�熸敹鐧�(f膩)鍣細鏀寔楂橀仈 32.75Gbps 鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛屾豢瓒崇従(xi脿n)浠ｉ�氫俊鍗�(xi茅)璀扮殑闇�姹�銆�
銆�銆�3. 闆嗘垚纭牳妯″锛氶泦鎴愪簡 PCIe Gen4 纭牳妯″锛岀啊鍖栦簡鑸囦富姗熺郴绲�(t菕ng)鐨勯�ｆ帴瑷▓銆�
銆�銆�4. 浣庡姛鑰楁灦妲嬶細閫氶亷鍎�(y艒u)鍖栭浕婧愮鐞嗘妧琛�锛屽湪淇濊瓑鎬ц兘鐨勫悓鏅傞檷浣庝簡鏁撮珨鍔熻�椼��
銆�銆�5. 寮峰ぇ鐨� DSP 鏀寔锛氬叿鍌欏ぇ閲� DSP Slice锛岄潪甯搁仼鍚堜俊铏熻檿鐞嗙浉闂滅殑閬嬬畻浠诲嫏銆�
銆�銆�6. 鍙潬鎬т繚闅滐細鏀寔绯鹃尟纰� (ECC) 鍔熻兘浠ュ寮锋暩(sh霉)鎿�(j霉)瀹屾暣鎬э紝鍚屾檪鎻愪緵浜嗗绋畨鍏ㄦ鍒朵繚璀风敤鎴� IP 鍜屾暩(sh霉)鎿�(j霉)銆�
XCVU11P-1FSGD2104E 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浜庢湇鍕欏櫒鍔犻��銆佸瓨鍎插劒(y艒u)鍖栧拰浜哄伐鏅鸿兘鎺ㄧ悊绛夊牬鏅�銆�
銆�銆�2. 閫氫俊鍩虹瑷柦锛氶仼鐢ㄤ簬 5G 鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鏁�(sh霉)鎿�(j霉)鍖呰檿鐞嗗強杞夌櫦(f膩)鍔熻兘銆�
銆�銆�3. 鑷嫊椐曢锛氱偤 ADAS 绯荤当(t菕ng)鎻愪緵瀵︽檪鍦栧儚铏曠悊鑳藉姏銆�
銆�銆�4. 閱�(y墨)鐧傝ō鍌欙細鏀寔楂樻�ц兘閱�(y墨)瀛稿奖鍍忓垎鏋愬拰瑷烘柗宸ュ叿闁嬬櫦(f膩)銆�
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬姗熷櫒瑕栬銆侀亱鍕曟帶鍒跺拰鍏朵粬闇�瑕佸揩閫熼熆鎳夌殑鎳夌敤涓�銆�
銆�銆�6. 杌嶄簨鑸囪埅澶╋細鎲戝�熷叾鍙潬鎬�锛岃鐢ㄤ綔闂滈嵉浠诲嫏鐠�(hu谩n)澧冧笅鐨勫祵鍏ュ紡铏曠悊鍣ㄦ垨鍗�(xi茅)铏曠悊鍣ㄣ��
XCVU9P-1FLGA2104E
銆�銆�XCVU7P-1FLGA2104E
銆�銆�XCVU5P-1FLGA2104E
