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XCVU11P-1FLGC2104I鏄疿ilinx鍏徃鎺ㄥ嚭鐨刄ltraScale+绯诲垪涓殑Virtex UltraScale+ FPGA鍨嬭櫉銆傝┎鑺墖鍩轰簬16nm宸ヨ棟鎶�琛�锛岄泦鎴愪簡澶ч噺鐨勫彲绶ㄧ▼閭忚集鍠厓銆佹暩(sh霉)瀛椾俊铏熻檿鐞嗭紙DSP锛夋ā濉婁互鍙婇珮閫熶覆琛屾敹鐧�(f膩)鍣紝閬╃敤浜庨珮鎬ц兘瑷堢畻銆佺恫(w菐ng)绲¤檿鐞�銆佹暩(sh霉)鎿�(j霉)涓績鍔犻�熷拰楂樼礆閫氫俊绯荤当(t菕ng)绛夊京闆滄噳鐢ㄩ牁鍩�銆�
銆�銆�閫欐FPGA鏀寔楂橀仈32Gbps鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛屽苟鎻愪緵璞愬瘜鐨勫閮ㄦ帴鍙ｉ伕闋�锛岃兘澶犳豢瓒冲悇绋京闆滅殑宓屽叆寮忕郴绲�(t菕ng)闇�姹�銆傚悓鏅�锛屽畠閭勫収宓屼簡寮峰ぇ鐨凙RM Cortex-A53铏曠悊鍣ㄩ櫍鍒楋紝浣垮緱鍏跺湪杌熺‖浠跺崝(xi茅)鍚岃ō瑷堟柟闈㈠叿鏈夌崹鐗瑰劒(y艒u)鍕�銆�
灏佽椤炲瀷锛欶LGC2104
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +125掳C
銆�銆�I/O 鏁�(sh霉)閲忥細绱�2104鍊�
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銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱�200钀��
銆�銆�瀛樺劜鍣ㄨ硣婧愶細绱�70MB鍒嗗竷寮忓拰濉奟AM
銆�銆�DSP Slice 鏁�(sh霉)閲忥細瓒呴亷5000鍊�
銆�銆�PCIE 鏀寔锛欸en4 x8
銆�銆�鏀剁櫦(f膩)鍣ㄥ付瀵細鏈�楂�32Gbps
XCVU11P-1FLGC2104I鍏峰倷浠ヤ笅闂滈嵉鐗规�э細
銆�銆�1. 楂樻�ц兘鏋舵锛氶噰鐢�16nm FinFET Plus宸ヨ棟鍒堕��锛屾彁渚涘崜瓒婄殑鎬ц兘鑸囧姛鑰楁瘮銆�
銆�銆�2. 澶ц(gu墨)妯￠倧杓硣婧愶細鎿佹湁绱�200钀�嬪彲绶ㄧ▼閭忚集鍠厓锛岄仼鍚堥亱琛屽京闆滅殑绠楁硶鍜屾暩(sh霉)鎿�(j霉)铏曠悊浠诲嫏銆�
銆�銆�3. 鍏у祵铏曠悊鍣細闆嗘垚闆欐牳ARM Cortex-A53铏曠悊鍣ㄥ瓙绯荤当(t菕ng)锛屾敮鎸佸鏅傛搷浣滅郴绲�(t菕ng)鍜岄珮绱氭帶鍒跺姛鑳�銆�
銆�銆�4. 璞愬瘜鐨勫瑷敮鎸侊細鏀寔澶氱ó妯欐簴鍗�(xi茅)璀�锛屽寘鎷琍CIe Gen4銆丆CIX銆丆PRI/LTE绛�銆�
銆�銆�5. 瀹夊叏鎬у寮凤細鏀寔AES-256鍔犲瘑鍜孯SA瑾嶈瓑锛屼繚璀风煡璀樼敘(ch菐n)娆婂強鏁忔劅鏁�(sh霉)鎿�(j霉)銆�
銆�銆�6. 闈堟椿鐨勮ō瑷堟祦绋嬶細鏀寔閮ㄥ垎閲嶉厤缃妧琛擄紝鍏佽ū鍕曟厠(t脿i)瑾挎暣绯荤当(t菕ng)鍔熻兘浠ラ仼鎳変笉鍚屾噳鐢ㄥ牬鏅殑闇�姹�銆�
銆�銆�7. 楂橀�熸敹鐧�(f膩)鍣細鎻愪緵澶氶仈鏁�(sh霉)鐧惧�嬮珮閬�32Gbps閫熺巼鐨勬敹鐧�(f膩)鍣ㄩ�氶亾锛岀敤浜庨�ｆ帴鍏朵粬瑷倷鎴栦氦鎻涙绔彛銆�
瑭插瀷铏熺殑FPGA寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浣滄湇鍕欏櫒璨犺級鍧囪 銆佹暩(sh霉)鎿�(j霉)鍖呰檿鐞嗗拰缍�(w菐ng)绲″畨鍏ㄥ姞閫�銆�
銆�銆�2. 閫氫俊鍩虹瑷柦锛氭敮鎸佷笅涓�浠ｇ劇绶氬熀绔�銆佹牳蹇冪恫(w菐ng)闂滃拰鍏夌簴鍌宠几瑷倷銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細瀵︾従(xi脿n)瀵︽檪鎺у埗銆佸湒鍍忚檿鐞嗗拰閬嬪嫊瑕�(gu墨)鍔�銆�
銆�銆�4. 閱�(y墨)鐧傛垚鍍忥細鐐鸿秴鑱叉尝銆丆T鎺冩弿鍎�鍜屽叾浠栭珮鍒嗚鲸鐜囪ê鏂峰伐鍏锋彁渚涘苟琛岃檿鐞嗚兘鍔涖��
銆�銆�5. 姹借粖闆诲瓙锛氬姪鍔汚DAS锛堥珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛夊拰鑷嫊椐曢骞宠嚭闁嬬櫦(f膩)銆�
銆�銆�6. 鑸┖鑸ぉ鑸囧湅闃诧細閬╃敤浜庨浄閬斾俊铏熻檿鐞�銆佽(w猫i)鏄熼�氫俊鍜屽皫鑸郴绲�(t菕ng)銆�
XCVU9P-2FLGA2104E
銆�銆�XCVU13P-2FLGA2104E
銆�銆�XCVU15P-2FLGA2104E
