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XCVU095-2FFVC2104I鏄疿ilinx鍏徃鎺ㄥ嚭鐨刅irtex UltraScale+绯诲垪FPGA鑺墖涓殑涓�鍊嬪瀷铏�銆傝┎绯诲垪灏堢偤楂樻�ц兘瑷堢畻銆佺恫绲¤檿鐞嗗拰鏁告摎涓績鍔犻�熸噳鐢ㄨ�岃ō瑷�锛屽叿鏈夐珮閭忚集瀵嗗害銆侀珮閫熶覆琛岄�ｆ帴鑳藉姏鍜屽挤澶х殑DSP鍔熻兘銆�
銆�銆�瑭茶姱鐗囬噰鐢�16nm FinFET宸ヨ棟鍒堕�狅紝鎻愪緵浜嗚睈瀵岀殑鍙法绋嬮倧杓硣婧愬拰纭牳IP妯″锛岃兘澶犳豢瓒冲京闆滅郴绲�(t菕ng)瑷▓鐨勯渶姹�銆�
绯诲垪锛歏irtex UltraScale+
銆�銆�鍨嬭櫉锛歑CVU095-2FFVC2104I
銆�銆�宸ヨ棟锛�16nm FinFET
銆�銆�閭忚集鍠厓鏁搁噺锛氱磩95钀��
銆�銆�RAM瀹归噺锛殈68Mbit
銆�銆�DSP Slice鏁搁噺锛氱磩5760鍊�
銆�銆�I/O寮曡叧鏁革細2104
銆�銆�閰嶇疆妯″紡锛歁aster/Slave SPI, SelectMAP, JTAG
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C to +100掳C
銆�銆�灏佽椤炲瀷锛欶FG2104
XCVU095-2FFVC2104I鍏锋湁闈炲父寮风殑鎬ц兘琛ㄧ従锛屾敮鎸侀珮閬�32.75Gbps鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛岄仼鐢ㄤ簬楂橀�熸暩鎿氬偝杓�銆�
銆�銆�瀹冮倓鍖呭惈澶ч噺闆嗘垚鐨勭‖鏍歌檿鐞嗗櫒濡侾CIe Gen4 x16鎺у埗鍣�銆丆CIX浜掕伅(li谩n)绛夛紝浠ョ啊鍖栭枊鐧�(f膩)骞舵彁楂樼郴绲�(t菕ng)鏁堢巼銆�
銆�銆�鍙﹀锛岃┎鍣ㄤ欢鏀寔楂樻晥鐨勫姛鑰楃鐞�锛屽苟鎻愪緵闈堟椿鐨勬檪閻樻灦妲嬩締鍎�(y艒u)鍖栨�ц兘鑸囧姛鑰椾箣闁撶殑骞宠 銆�
銆�銆�姝ゅ锛屾FPGA鍙互鍒╃敤Xilinx鐨刅ivado瑷▓濂椾欢閫茶闁嬬櫦(f膩)锛屾彁渚涘緸RTL缍滃悎鍒版瘮鐗规祦鐢熸垚鐨勫畬鏁存祦绋嬫敮鎸�銆�
閫欐FPGA閬╁悎鐢ㄤ簬闇�瑕佹サ楂樻�ц兘鍜屼綆寤堕伈鐨勬噳鐢ㄥ牬鏅腑锛屼緥濡傦細
銆�銆�1. 缍茬怠璺敱鍣ㄥ拰浜ゆ彌姗熺殑鏍稿績铏曠悊妯″锛�
銆�銆�2. 楂橀�熸暩鎿氶噰闆嗚垏淇¤櫉铏曠悊绯荤当(t菕ng)锛�
銆�銆�3. 鏁告摎涓績鏈嶅嫏鍣ㄥ収鐨勫姞閫熷崱绲勪欢锛�
銆�銆�4. 閱�(y墨)鐧傛垚鍍忚ō鍌欎腑鐨勫湒鍍忚檿鐞嗗柈鍏�锛�
銆�銆�5. 閫氫俊鍩虹瑷柦涓殑鍩哄付铏曠悊骞宠嚭绛�銆�
XCVU095-1FFVC2104E,
銆�銆�XCVU095-2FFVC1760I,
銆�銆�XCVU095-1FFVC1760E
