鍨嬭櫉锛歑CVU095-2FFVC1517E
銆�銆�宸ヨ棟锛�16nm
銆�銆�閭忚集鍠�鍏冿��95K
銆�銆�閰嶇疆闁冨瓨锛氬�栫��
銆�銆�瀛樺劜濉婏細28.8MB
銆�銆�DSP Slice 鏁�(sh霉)閲忥細5880
銆�銆�I/O 鏁�(sh霉)閲忥細1232
銆�銆�鏈�澶у伐浣滈牷鐜囷細~1GHz
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 32.75Gbps
銆�銆�渚涢浕闆诲�擄��0.8V 鏍稿績锛�1.0V 杓斿姪闆昏矾
銆�銆�灏佽�濓細FFVC1517

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銆�銆�鍙﹀��锛孹CVU095 鎻愪緵浜嗛潏娲荤殑鏅傞悩绠＄悊宸ュ叿锛圕lock Management Tile锛夛紝鍖呮嫭 PLL 鍜� MMCM 妯″��锛屾湁鍔╀簬鐢熸垚绮剧⒑涓斾綆鎶栧嫊鐨勬檪閻樹俊铏�銆傛渶鍚�锛孹ilinx 鎻愪緵浜嗗畬鏁寸殑闁嬬櫦(f膩)鐠�(hu谩n)澧� Vivado锛屽公鍔╁伐绋嬪斧蹇�閫熶笂鎵嬪苟鍎�(y艒u)鍖栬ō(sh猫)瑷堟祦绋�銆�

瑭插瀷铏� FPGA 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 楂橀�熺恫(w菐ng)绲�(lu貌)浜ゆ彌姗熻垏璺�鐢卞��
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銆�銆�3. 瑕栭牷寤ｆ挱瑷�(sh猫)鍌欏強鍦栧儚铏曠悊绯荤当(t菕ng)
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銆�銆�5. 宸ユキ(y猫)鑷�鍕曞寲鎺у��
銆�銆�6. ADAS锛堥珮绱氶�曢�涜紨鍔╃郴绲�(t菕ng)锛夊拰鑷�鍕曢�曢�涚浉闂�(gu膩n)纭�浠�
銆�銆�7. 鐒＄窔閫氫俊鍩虹��(ch菙)瑷�(sh猫)鏂斤紝渚嬪�� 5G 鍩虹珯
銆�銆�8. 鍔犲瘑璨ㄥ梗鎸栫う ASIC 鍘熷瀷椹楄瓑骞宠嚭
銆�銆�鐢变簬鍏跺挤澶х殑鍔熻兘闆嗗悎鍜屾摯灞曡兘鍔�锛孹CVU095-2FFVC1517E 鎴愮偤鐪惧�氬��(f霉)闆滈浕瀛愮郴绲�(t菕ng)鐨勭悊鎯抽伕鎿�銆�

XCVU095-1FFVC1517E
銆�銆�XCVU095-3FFVC1517E