鏅傞枔锛�2025/5/13 14:59:13
闁辫畝锛�24
XCKU15P-1FFVA1760E 鏄竴娆剧敱 Xilinx 鍏徃鐢熺敘(ch菐n)鐨� Kintex UltraScale 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛夈�傝┎绯诲垪鍣ㄤ欢灏堢偤楂樻�ц兘銆佷綆鍔熻�楁噳鐢ㄨ�岃ō瑷堬紝閬╃敤浜庨�氫俊銆佸唬鎾闋�銆佹脯瑭﹁垏娓噺浠ュ強杌嶄簨绛夐牁(l菒ng)鍩熺殑寰╅洔淇¤櫉铏曠悊浠诲嫏銆�
銆�銆�閫欐 FPGA 鍩轰簬 20nm 鍒剁▼鎶�琛�(sh霉)鍒堕��锛屽叿鍌欏挤澶х殑閭忚集璩囨簮鍜� DSP 鐗囷紝鍚屾檪闆嗘垚浜嗛珮閫熶覆琛屾敹鐧�(f膩)鍣�锛岃兘澶犳豢瓒抽珮甯跺鏁�(sh霉)鎿�(j霉)鍌宠几?sh霉)鐢锋灗?銆傛澶�锛屽畠閭勬敮鎸佸绋帴鍙ｆ婧�锛屽苟鎻愪緵闈堟椿鐨� I/O 閰嶇疆銆�
鍨嬭櫉锛歑CKU15P-1FFVA1760E
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛欿intex UltraScale
銆�銆�鍒剁▼宸ヨ棟锛�20nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 15,360 鍊� CLB锛堥厤缃倧杓锛�
銆�銆�DSP Slice 鏁�(sh霉)閲忥細900 鍊�
銆�銆�RAM 璩囨簮锛氱磩 4.7Mb 鍒嗗竷寮� RAM 鍜屽 RAM
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄦ暩(sh霉)閲忥細32 鍊�
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂樺彲閬� 16.3Gbps
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細1760 鍊�
銆�銆�灏佽椤炲瀷锛欶FGA1760
銆�銆�宸ヤ綔闆诲锛氭牳蹇冮浕澹� 0.85V锛孖/O 闆诲 1.0V 鎴� 1.8V
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XCKU15P-1FFVA1760E 鎻愪緵浜嗚睈瀵岀殑纭欢璩囨簮鍜屽厛閫茬殑鏋舵(g貌u)鐗归粸锛�
銆�銆�1. 楂樻�ц兘锛氶噰鐢� UltraScale 鏋舵(g貌u)锛屽劒(y艒u)鍖栦簡鑺墖鍏�(n猫i)閮ㄤ簰閫ｇ祼(ji茅)妲�(g貌u)锛岄’钁楁彁鍗囦簡鏅傞悩闋荤巼鍜屽悶鍚愰噺銆�
銆�銆�2. DSP 铏曠悊鑳藉姏锛氬収(n猫i)缃ぇ閲� DSP Slice锛屽彲浠ラ珮鏁堝鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗙畻娉�锛屽 FFT銆佹烤娉㈠櫒鍜岀煩闄ｉ亱绠楃瓑銆�
銆�銆�3. 楂橀�熼�ｆ帴锛氭敮鎸侀珮閬� 16.3Gbps 鐨勯珮閫熸敹鐧�(f膩)鍣�锛岄仼鍚堢敤浜� PCIe Gen3銆丆PRI 鍜� JESD204B 鎺ュ彛銆�
銆�銆�4. 鍏�(n猫i)瀛樺閲忥細鍖呭惈澶у閲忕殑宓屽叆寮� RAM锛屽彲鐢ㄤ簬瀵︾従(xi脿n) FIFO銆佺珐瀛樺拰鍏朵粬瀛樺劜鍔熻兘銆�
銆�銆�5. 鍙摯灞曟�э細鏀寔閫氶亷 AXI 鎺ュ彛鑸囧叾浠栬檿鐞嗗櫒鎴栧姞閫熷櫒鍗�(xi茅)鍚屽伐浣溿��
銆�銆�6. 鍔熻�楃鐞嗭細鍏锋湁鍕曟厠(t脿i)鍔熻�楄(di脿o)绡�(ji茅)鍔熻兘锛屽彲鏍规摎(j霉)瀵﹂殯闇�姹傞檷浣庨枒缃ā濉婄殑宸ヤ綔闋荤巼浠ョ瘈(ji茅)鐪佽兘婧愩��
銆�銆�7. 瀹夊叏鎬э細鏀寔澶氱ó鍔犲瘑妯欐簴锛屽寘鎷� AES 鍜� SHA锛岀⒑淇濇暩(sh霉)鎿�(j霉)鐨勫畨鍏ㄥ偝杓稿拰瀛樺劜銆�
瑭插瀷铏熺殑 FPGA 寤ｆ硾鎳夌敤浜庡鍊嬮牁(l菒ng)鍩燂細
銆�銆�1. 閫氫俊瑷倷锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑淇¤櫉铏曠悊鍜屽崝(xi茅)璀拌綁(zhu菐n)鎻�銆�
銆�銆�2. 瑕栭牷铏曠悊锛氱敤浜庡鏅傚湒鍍忓寮�銆佹牸寮忚綁(zhu菐n)鎻涘拰澹撶府瑙ｅ绺搷浣溿��
銆�銆�3. 娓│鑸囨脯閲忓剙鍣細渚嬪绀烘尝鍣�銆佷俊铏熺櫦(f膩)鐢熷櫒涓姹傚揩閫熸暩(sh霉)鎿�(j霉)閲囬泦鍜屽垎鏋愮殑閮ㄥ垎銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ綔閬嬪嫊鎺у埗绯荤当(t菕ng)鐨勪富鎺у柈鍏冩垨鏅鸿兘鍌虫劅鍣ㄧ殑鏁�(sh霉)鎿�(j霉)铏曠悊鍣�銆�
銆�銆�5. 姹借粖闆诲瓙锛氬湪楂樼礆椐曢杓斿姪绯荤当(t菕ng)锛圓DAS锛変腑瀹屾垚瑕栬璀樺垾鍜屾焙绛栬▓绠椾换鍕�銆�
銆�銆�6. 閱�(y墨)鐧傛垚鍍忥細鏀寔瓒呰伈娉��丆T 鎺冩弿鍎�绛夐啱(y墨)鐧傝ō鍌欎腑鐨勫湒鍍忛噸寤虹畻娉�銆�
XCKU10P-1FFVA1156E
銆�銆�XCKU15P-1FFVB1760E
銆�銆�XCKU15P-2FFVA1760E
