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XCKU11P-3FFVA1156E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Kintex UltraScale 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏�銆傝┎绯诲垪灏堢偤楂樻�ц兘銆佷綆鍔熻�楁噳鐢ㄨō瑷�锛屽唬娉涙噳鐢ㄤ簬閫氫俊銆佹暩鎿氫腑蹇冦�佸伐妤�(y猫)鍜岄啱(y墨)鐧傜瓑闋樺煙銆侹intex UltraScale 绯诲垪閫氶亷鍏跺劒(y艒u)鍖栫殑鏋舵鍜岃睈瀵岀殑璩囨簮锛屽湪鎬ц兘鑸囨垚鏈箣闁撻仈鍒颁簡鑹ソ鐨勫钩琛�銆�
銆�銆�姝よ姱鐗囬噰鐢ㄥ厛閫茬殑 FinFET 宸ヨ棟鍒堕��锛屾彁渚涢珮閭忚集瀵嗗害銆侀珮閫熶覆琛岄�ｆ帴鑳藉姏浠ュ強闈堟椿鐨� I/O 閰嶇疆锛岄潪甯搁仼鍚堥渶瑕侀珮鍚炲悙閲忓拰浣庡欢閬茬殑鎳夌敤鍫存櫙銆�
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銆�銆�绯诲垪锛欿intex UltraScale
銆�銆�宸ヨ棟鍒剁▼锛�16nm
銆�銆�閰嶇疆閭忚集鍠厓锛圕LB锛夛細绱� 174,500
銆�銆�DSP Slice 鏁搁噺锛�2880
銆�銆�Block RAM 鏁搁噺锛�1395
銆�銆�UltraRAM 鏁搁噺锛�118.5Mb
銆�銆�PCIe 鏀寔锛欸en3 x8
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼锛氭渶楂� 16.3 Gbps
銆�銆�I/O Bank 鏁搁噺锛�42
銆�銆�灏佽椤炲瀷锛欶FVA1156
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XCKU11P-3FFVA1156E 鎻愪緵浜嗗挤澶х殑铏曠悊鑳藉姏鍜岃睈瀵岀殑澶栬ō鏀寔銆傚畠鍏锋湁浠ヤ笅椤憲鐗归粸锛�
銆�銆�1. 楂樻�ц兘閭忚集绲愭锛氬熀浜� UltraScale 鏋舵锛岃兘澶犲鐝惧京闆滅殑鏁稿瓧淇¤櫉铏曠悊鍜屾暩鎿氳矾寰戝劒(y艒u)鍖栥��
銆�銆�2. 寮峰ぇ鐨� DSP 鍔熻兘锛氬収缃ぇ閲� DSP Slice锛岄仼鐢ㄤ簬鐭╅櫍閬嬬畻銆佹烤娉㈠櫒鍜屽叾浠栬▓绠楀瘑闆嗗瀷浠诲嫏銆�
銆�銆�3. 澶у閲忓瓨鍎茶硣婧愶細閰嶅倷 Block RAM 鍜� UltraRAM锛屾豢瓒冲ぇ瑕�(gu墨)妯℃暩鎿氱珐瀛橀渶姹傘��
銆�銆�4. 楂橀�熶覆琛屾帴鍙ｏ細鏀寔楂橀仈 16.3Gbps 鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛岄仼鍚堥珮閫熸暩鎿氬偝杓�銆�
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銆�銆�6. 浣庡姛鑰楄ō瑷堬細閲囩敤 16nm 鍒剁▼鎶�琛�锛屾湁鏁堥檷浣庡姛鑰楁按骞�銆�
銆�銆�7. 寤ｆ硾鐨勬噳鐢ㄩ仼閰嶆�э細鏀寔寰為�氫俊鍩虹瑷柦鍒板祵鍏ュ紡瑕栬绛夊绋噳鐢ㄥ牬鏅��
瑭插瀷铏� FPGA 涓昏鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 鐒＄窔閫氫俊鍩虹珯锛氬 LTE/5G 鍩虹珯涓敤浣滃熀甯惰檿鐞嗗柈鍏�銆�
銆�銆�2. 鏁告摎涓績鍔犻�燂細鐢ㄤ簬缍茬怠鍔熻兘铏涙摤鍖栵紙NFV锛�銆佹繁搴﹀缈掓帹鐞嗙瓑浠诲嫏銆�
銆�銆�3. 瑕栭牷铏曠悊锛氭敮鎸侀珮娓呰闋荤法纰艰В纰笺�佸湒鍍忓寮风瓑鍔熻兘銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細瀵︽檪鎺у埗銆侀亱鍕曟帶鍒跺強寰╅洔绯荤当(t菕ng)鐩�(ji膩n)鎺с��
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銆�銆�6. 娓│娓噺锛氶珮閫熸暩鎿氶噰闆嗚垏鍒嗘瀽绯荤当(t菕ng)銆�
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