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XCKU11P-2FFVA1156E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Kintex UltraScale 绯诲垪 FPGA 鑺墖锛屽爆浜庨珮鎬ц兘銆佷綆鍔熻�楃殑 FPGA 骞宠嚭銆傝┎绯诲垪鑺墖寤ｆ硾鎳夌敤浜庨�氫俊銆佽埅绌鸿埅澶�銆佸伐妤�(y猫)鑷嫊鍖栦互鍙婂唬鎾闋荤瓑闋樺煙銆�
銆�銆�姝ゅ瀷铏熶腑鐨� 'XCKU' 琛ㄧず Kintex UltraScale 绯诲垪锛�'11P' 浠ｈ〃鍏烽珨鐨勭敘鍝佺瓑绱氬拰閭忚集鍠厓瑕�(gu墨)妯�锛�'-2' 琛ㄧず閫熷害绛夌礆锛�'FFVA1156' 琛ㄧず灏佽椤炲瀷鍙婂紩鑵虫暩(sh霉)銆�
绯诲垪锛欿intex UltraScale
銆�銆�鍨嬭櫉锛歑CKU11P
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�灏佽锛欶FVA1156
銆�銆�閭忚集鍠厓锛氱磩 83940 鍊�
銆�銆�RAM 瀹归噺锛氱磩 32.7 Mb
銆�銆�DSP 妯″鏁�(sh霉)閲忥細绱� 1820 鍊�
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶氭敮鎸� 840 鍊�
銆�銆�閰嶇疆妯″紡锛氫富寰� SPI銆丅PI 鍜屽叾浠栧父瑕嬫ā寮�
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 85掳C锛�
XCKU11P-2FFVA1156E 鎻愪緵浜嗗挤澶х殑铏曠悊鑳藉姏鍜岄潏娲绘��銆傚畠鍏锋湁澶ч噺鐨� DSP Slice锛屽彲鐢ㄤ簬寰╅洔瑷堢畻浠诲嫏锛屽淇¤櫉铏曠悊鍜屾鍣ㄥ缈掔畻娉曞姞閫�銆�
銆�銆�鑺墖鍏х疆澶у閲� Block RAM 鍜屽垎甯冨紡 RAM锛岄仼鍚堟暩(sh霉)鎿�(j霉)绶╁瓨鍜屽瓨鍎查渶姹�銆�
銆�銆�鍏� UltraScale 鏋舵閫氶亷鏀归�茬殑浜掗�ｆ妧琛撻’钁楁彁楂樹簡鎬ц兘鍜屽付瀵埄鐢ㄧ巼銆�
銆�銆�鍚屾檪鏀寔 PCIe銆佸崈鍏嗕互澶恫绛夊绋珮閫熸帴鍙ｅ崝(xi茅)璀�锛屼究浜庢寤哄京闆滅殑绯荤当(t菕ng)绱氳ō瑷�銆�
銆�銆�姝ゅ锛岃┎鍣ㄤ欢鍏峰倷鍕曟厠(t脿i)鍔熻兘鍒囨彌 (DRC) 鎶�琛�锛屽厑瑷遍儴鍒嗛噸鏂伴厤缃紝寰炶�屽劒(y艒u)鍖栧姛鑰楄垏璩囨簮鍒╃敤銆�
瑭插瀷铏� FPGA 涓昏閬╃敤浜庨渶瑕侀珮鍚炲悙閲忓拰浣庡欢閬茬殑鍫存櫙锛屼緥濡傦細
銆�銆�1. 鐒＄窔閫氫俊鍩虹珯涓熀甯惰檿鐞嗗柈鍏冪殑瑷▓銆�
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銆�銆�4. 宸ユキ(y猫)鎺у埗闋樺煙涓殑閬嬪嫊鎺у埗鍜岃瑕烘娓��
銆�銆�5. 鏁�(sh霉)鎿�(j霉)涓績鐨勭恫绲′氦鎻涙鍜岃矾鐢卞櫒瀵︾従(xi脿n)銆�
銆�銆�6. 瑕栭牷鐩�(ji膩n)鎺х郴绲�(t菕ng)涓殑鍦栧儚绶ㄧ⒓瑙ｇ⒓鍜屽寮枫��
XCKU11P-2FFVB1156E
銆�銆�XCKU11P-2FFVC1156E
