鍨嬭櫉(h脿o)锛歑CKU095-2FFLVE1924I
銆�銆�宸ヨ棟锛�20nm
銆�銆�閰嶇疆妯″紡锛氫富寰為厤缃�
銆�銆�鍏�(n猫i)鏍搁浕澹擄細1.0V
銆�銆�I/O闆诲�擄��1.8V/2.5V/3.3V
銆�銆�灏佽�濆舰寮忥細FFLVE1924
銆�銆�閭忚集鍠�鍏冿細绱� 95K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2300
銆�銆�Block RAM锛氱磩 6144KB
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄦ暩(sh霉)閲忥細32
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂樺彲閬�(d谩) 28Gbps

XCKU095-2FFLVE1924I 鎻愪緵浜嗗挤(qi谩ng)澶х殑鎬ц兘鑸囬潏娲绘��銆俇ltraScale 鏋舵��(g貌u)閫氶亷鏀归��(j矛n)鐨勮矾鐢辨��(j墨)鍒跺拰鏇撮珮鏁堢殑鏅�(sh铆)閻樼�＄悊鎶�琛�(sh霉)锛岄’钁楁彁鍗囦簡鑺�鐗囩殑宸ヤ綔闋荤��銆�
銆�銆�姝ゅ��锛岃┎ FPGA 闆嗘垚浜嗗ぇ閲忕‖鏍� IP 妯″��锛屽�� PCIe Gen3銆�100G Ethernet 鍜� Interlaken 绛�锛岀啊(ji菐n)鍖栦簡寰�(f霉)闆滅殑鎺ュ彛瑷�(sh猫)瑷�(j矛)娴佺▼銆�
銆�銆�鍦ㄥ姛鑰楀劒(y艒u)鍖栨柟闈�锛孹CKU095 寮曞叆浜嗗嫊(d貌ng)鎱�(t脿i)鍔熻�楄��(di脿o)绡�(ji茅)鍔熻兘锛屽彲鏍规摎(j霉)瀵�(sh铆)闅涜矤(f霉)杓夎��(di脿o)鏁村伐浣滈浕澹撲互闄嶄綆鏁撮珨鑳借��銆�
銆�銆�瑭茶姱鐗囬倓鏀�鎸佸�氱ó瀛樺劜(ch菙)鍣ㄦ帴鍙ｆ��(bi膩o)婧�(zh菙n)锛屽寘鎷� DDR4銆丷LDRAM3 鍜� QDRII+ 绛�锛岄��(j矛n)涓�姝ュ�炲��(qi谩ng)浜嗗叾閬╃敤鑼冨湇銆�

XCKU095-2FFLVE1924I 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬闇�瑕侀珮鎬ц兘铏曠悊鑳藉姏鐨勯牁(l菒ng)鍩�銆備緥濡傦細
銆�銆�- 鏈夌窔鍜岀劇绶氶�氫俊鍩虹��(ch菙)瑷�(sh猫)鏂戒腑鐨勪俊铏�(h脿o)铏曠悊浠诲嫏(w霉)
銆�銆�- 鏁�(sh霉)鎿�(j霉)涓�蹇冨姞閫熷崱涓婄殑鏁�(sh霉)鎿�(j霉)鍖呰檿鐞嗚垏鍔犲瘑瑙ｅ瘑鎿嶄綔
銆�銆�- 閱�(y墨)鐧傛垚鍍忚ō(sh猫)鍌欎腑鐨勫湒鍍忛噰闆嗚垏瀵�(sh铆)鏅�(sh铆)铏曠悊鍔熻兘
銆�銆�- 鑸�绌鸿埅澶╅��(l菒ng)鍩熶腑鐨勫皫(d菐o)鑸�鎺у埗鍙婇仚鎰熸��(sh霉)鎿�(j霉)铏曠悊
銆�銆�- 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栫郴绲�(t菕ng)涓�鐨勯��(y霉n)鍕�(d貌ng)鎺у埗鑸囨��(j墨)鍣ㄨ�栬�虹畻娉曞��(sh铆)鐝�(xi脿n)

XCKU060-2FFLVE1517E, XCKU115-2FFLGA1760I