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XCKU085-1FLVF1924I鏄疿ilinx鍏徃鎺ㄥ嚭鐨凨intex UltraScale绯诲垪FPGA鍣ㄤ欢锛岄噰鐢�20nm宸ヨ棟鍒堕��銆傝┎绯诲垪FPGA閬╃敤浜庨�氫俊銆佹暩(sh霉)鎿�(j霉)涓績銆佸唬鎾闋�銆佸伐妤�(y猫)鍜岄啱(y墨)鐧傜瓑澶氬�嬮牁鍩�銆傛鍨嬭櫉鍏锋湁楂橀倧杓瘑搴�銆侀珮鎬ц兘鏀剁櫦(f膩)鍣ㄤ互鍙婇潏娲荤殑I/O閰嶇疆锛岄仼鍚堥渶瑕侀珮甯跺鍜屽京闆滀俊铏熻檿鐞嗙殑鎳夌敤鍫存櫙銆�
銆�銆�Kintex UltraScale绯诲垪鍦ㄥ姛鑰楄垏鎬ц兘涔嬮枔鍙栧緱浜嗚壇濂界殑骞宠 锛屽悓鏅傛彁渚涗簡璞愬瘜鐨凞SP Slice璩囨簮銆丅lock RAM鍜屽祵鍏ュ紡瀛樺劜鍣ㄩ伕闋咃紝鏀寔鐢ㄦ埗瀵︾従(xi脿n)寰╅洔鐨勭畻娉曡ō瑷堝拰鏁�(sh霉)鎿�(j霉)铏曠悊浠诲嫏銆�
鍨嬭櫉锛歑CKU085-1FLVF1924I
銆�銆�灏佽锛�1924-Pin FCLGA
銆�銆�宸ヨ棟锛�20nm
銆�銆�閭忚集鍠厓鏁�(sh霉)锛氱磩85k鍊婼lice
銆�銆�DSP Slice鏁�(sh霉)閲忥細3600鍊�
銆�銆�鍏ч儴RAM瀹归噺锛氱磩10.8Mb
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂樺彲閬�32.75Gbps
銆�銆�I/O Bank鏁�(sh霉)閲忥細32鍊�
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C鑷�+100掳C锛堝晢妤�(y猫)绱氾級
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹撶偤0.9V锛岃紨鍔╅浕澹撶偤1.0V鎴�1.8V
XCKU085-1FLVF1924I鍏锋湁浠ヤ笅涓昏鐗规�э細
銆�銆�1. 楂樻�ц兘鏀剁櫦(f膩)鍣細鏀寔澶氱ó涓茶鍗�(xi茅)璀版婧�锛屽PCIe Gen3銆丆PRI銆丣ESD204B绛�銆�
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銆�銆�5. 鍏х疆纭牳妯″锛氶儴鍒嗗瀷铏熸敮鎸侀泦鎴愮‖鏍歌檿鐞嗗櫒锛堝ARM Cortex-A53锛�锛屼絾鏈瀷铏熸湭鍖呭惈姝ら纭牳銆�
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銆�銆�7. 浣庡姛鑰楄ō瑷堬細閲囩敤UltraScale鏋舵鍎�(y艒u)鍖栧姛鑰楄〃鐝�(xi脿n)锛岄仼鍚堝皪鍔熻�楁晱鎰熺殑鎳夌敤鐠�(hu谩n)澧冦��
XCKU085-1FLVF1924I寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1銆佸洖鍌崇恫(w菐ng)绲¤ō鍌欏拰璺敱鍣�銆�
銆�銆�2. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鐢ㄤ簬鏈嶅嫏鍣ㄨ矤杓夊潎琛�銆佹暩(sh霉)鎿�(j霉)鍖呰檿鐞嗗拰鍔犲瘑瑙ｅ瘑浠诲嫏銆�
銆�銆�3. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鏀寔瀵︽檪楂樻竻瑕栭牷绶ㄧ⒓瑙ｇ⒓鍙婂湒褰㈡覆鏌�銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細閬╃敤浜庡伐妤�(y猫)鎺у埗銆佹鍣ㄤ汉瑕栬鍜岄亱鍕曟帶鍒�銆�
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銆�銆�6. 娓│娓噺锛氬彲鐢ㄤ簬楂橀�熸暩(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)鍜屼俊铏熷垎鏋愬剙銆�
XCKU060-1FFVA1156E, XCKU115-2FLVB1517I
