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XCKU040-3FFVA1156C 鏄竴娆剧敱 Xilinx 鍏徃鐢熺敘鐨� Kintex UltraScale 绯诲垪 FPGA 鑺墖銆傝┎绯诲垪鑺墖閬╃敤浜庨珮甯跺銆佷綆寤堕伈鐨勬噳鐢ㄥ牬鏅�锛屼緥濡傜恫绲¤檿鐞�銆佷俊铏熻檿鐞嗗拰鏁告摎涓績鍔犻�熺瓑銆侹intex UltraScale 绯诲垪浠ュ劒(y艒u)鐣扮殑鎬у児姣斿拰楂樻�ц兘钁楃ū锛岃兘澶犳彁渚涢潏娲荤殑瑷▓鏂规銆�
銆�銆�Kintex UltraScale 绯诲垪鍩轰簬鑷虹⿳闆伙紙TSMC锛夌殑 16nm FinFET+ 宸ヨ棟鍒堕��锛屽叿鍌欐洿楂樼殑闆嗘垚搴﹀拰鏇翠綆鐨勫姛鑰�銆俋CKU040-3FFVA1156C 鐗瑰垾閬╁悎闇�瑕佷腑绛夐倧杓硣婧�銆侀珮 I/O 鏁搁噺鍜岄珮閫熶覆琛岄�ｆ帴鐨勬噳鐢ㄥ牬鍚�銆�
鍨嬭櫉锛歑CKU040-3FFVA1156C
銆�銆�灏佽锛欶FVA1156
銆�銆�閫熷害绛夌礆锛�-3
銆�銆�閭忚集鍠厓鏁革細绱� 40,800 鍊� CLB Slice
銆�銆�RAM 璩囨簮锛氱磩 27.5Mb
銆�銆�DSP Slice 鏁搁噺锛�2,520
銆�銆�閰嶇疆妯″紡锛歋electMAP 鍜� JTAG
銆�銆�I/O Bank 鏁搁噺锛�29
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
1. 鍩轰簬 16nm FinFET+ 宸ヨ棟鍒堕��锛屾彁渚涘嚭鑹茬殑鎬ц兘鑸囪兘鏁堟瘮銆�
銆�銆�2. 闆嗘垚浜嗚睈瀵岀殑 DSP Slice 鍜� Block RAM 璩囨簮锛屾敮鎸佸京闆滅殑绠楁硶瀵︾従銆�
銆�銆�3. 鏀寔楂橀仈 32.75Gbps 鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛屾豢瓒抽珮閫熸暩鎿氬偝杓搁渶姹�銆�
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銆�銆�5. 鍏х疆寮峰ぇ鐨勮瑭﹀拰鐩�(ji膩n)鎺у姛鑳�锛屼緥濡� Vivado 涓殑 ChipScope 宸ュ叿鏀寔銆�
銆�銆�6. 鍙伕澶氱ó閰嶇疆妯″紡锛屼究浜庝笉鍚屾噳鐢ㄥ牬鏅笅鐨勭郴绲辫ō瑷�銆�
銆�銆�7. 鏀寔 Xilinx 鐨� Vivado Design Suite 闁嬬櫦(f膩)鐠�(hu谩n)澧冿紝鎻愪緵楂樻晥鐨勯枊鐧�(f膩)楂旈銆�
銆�銆�8. 閲囩敤楂樺紩鑵虫暩 BGA 灏佽锛團FVA1156锛夛紝閬╂噳寰╅洔鐨勯浕璺澘甯冨眬闇�姹�銆�
銆�銆�9. 寤ｆ硾鎳夌敤浜庨�氫俊銆佸伐妤�(y猫)銆侀啱(y墨)鐧�銆佹苯杌婂拰鑸┖鑸ぉ绛夐牁鍩�銆�
1. 楂橀�熺恫绲￠�氫俊瑷倷涓殑鏁告摎鍖呰檿鐞嗗拰鍗旇杞夋彌銆�
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銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栫郴绲变腑鐨勫鏅傛帶鍒跺拰鍌虫劅鍣ㄦ帴鍙�銆�
銆�銆�5.铏曠悊浠诲嫏銆�
銆�銆�6. 鐒＄窔鍩虹瑷柦寤鸿ō涓殑鍩哄付铏曠悊鍜屾尝鏉熸垚褰㈡妧琛撳鐝�銆�
銆�銆�7. 娓│娓噺瑷倷涓殑楂橀�熶俊铏熺敓鎴愯垏鍒嗘瀽銆�
銆�銆�8. 瑕栭牷寤ｆ挱闋樺煙鐨勫鏅傜法纰艰垏瑙ｇ⒓铏曠悊銆�
銆�銆�9. 瀹夊叏鐩�(ji膩n)鎺х郴绲辩殑鍦栧儚澹撶府鑸囧姞瀵嗗姛鑳藉鐝�銆�
XCKU040-2FFVA1156I
銆�銆�XCKU040-2FFVA1156E
銆�銆�XCKU040-2FFVB784E
