鏅傞枔锛�2025/4/30 18:32:21
闁辫畝锛�30
XC7Z100-FFG900ACX 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Zynq-7000 绯诲垪鐨勫彲绶ㄧ▼鐗囦笂绯荤当(t菕ng) (SoC) 鑺墖锛岃┎绯诲垪铻嶅悎浜� ARM Cortex-A9 闆欐牳铏曠悊鍣ㄨ垏 FPGA 鐨勫彲绶ㄧ▼閭忚集璩囨簮銆傞�欎竴绲勫悎浣垮緱 XC7Z100 鎴愮偤闇�瑕侀珮鎬ц兘瑷堢畻鍜屽畾鍒剁‖浠跺姞閫熺殑鎳夌敤鐨勭悊鎯抽伕鎿�銆�
銆�銆�瑭插櫒浠跺叿鏈夎睈瀵岀殑澶栬ō鎺ュ彛鍜岄潏娲荤殑 I/O 閰嶇疆鑳藉姏锛岄仼鍚堢敤浜庡祵鍏ュ紡绯荤当(t菕ng)銆佸伐妤�(y猫)鑷嫊鍖�銆侀�氫俊瑷倷浠ュ強娑堣不椤為浕瀛愮敘(ch菐n)鍝佺瓑闋樺煙銆�
鍨嬭櫉锛歑C7Z100
銆�銆�灏佽锛欶FG900
銆�銆�閫熷害绛夌礆锛欰CX
銆�銆�FPGA 閭忚集鍠厓鏁�(sh霉)锛氱磩 235,000
銆�銆�ARM 铏曠悊鍣細闆欐牳 Cortex-A9
銆�銆�涓婚牷锛氭渶楂樺彲閬� 667 MHz
銆�銆�瀛樺劜鍣細楂橀仈 9 MB 鐨� Block RAM 鍜� 1.4 MB 鐨勫垎甯冨紡 RAM
銆�銆�鏀寔鐨� DDR 鍏�(n猫i)瀛橀鍨嬶細DDR3/DDR3L
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Slave Parallel, Master SPI, BPI, JTAG
銆�銆�婧害鑼冨湇锛氬晢妤�(y猫)绱� (-10掳C 鑷� +85掳C)
銆�銆�I/O 鏁�(sh霉)閲忥細澶氶仈 896 鍊嬬敤鎴跺彲鐢� I/O
銆�銆�鍔熻�楋細鍏稿瀷鍊肩磩鐐� 3W锛堢┖闁戠媭鎱�(t脿i)锛�
XC7Z100-FFG900ACX 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 闆欐牳 ARM Cortex-A9 MPCore 铏曠悊鍣ㄥ瓙绯荤当(t菕ng)锛屾敮鎸� NEON 鍜屾诞榛為亱绠楀柈鍏冿紝鎻愪緵寮峰ぇ鐨勯�氱敤瑷堢畻鑳藉姏銆�
銆�銆�2. FPGA 鍙法绋嬮倧杓儴鍒嗗寘鍚ぇ閲� CLB锛圕onfigurable Logic Blocks锛夈�丏SP Slice 鍜� Block RAM锛岃兘澶�?q奴)宕縁(xi脿n)鑷畾缇╃‖浠跺姞閫熸ā濉�銆�
銆�銆�3. 鎻愪緵璞愬瘜鐨勫瑷帴鍙�锛屼緥濡� Gigabit Ethernet銆乁SB銆丼DIO 鍜� PCIe 绛�锛屾敮鎸佸绋�氫俊鍗�(xi茅)璀�銆�
銆�銆�4. 鏀寔 AXI 绺界窔鏋舵锛屾柟渚胯檿鐞嗗櫒鑸� FPGA 閭忚集涔嬮枔鐨勯珮鏁堟暩(sh霉)鎿�(j霉)鍌宠几銆�
銆�銆�5. 鍏�(n猫i)缃帠鐩哥挵(hu谩n) (PLL) 鍜屾檪閻樼鐞嗘ā濉�锛屾彁渚涢潏娲荤殑鏅傞悩鍒嗛厤鍜岀鐞嗗姛鑳姐��
銆�銆�6. 鎻愪緵澶氱ó闆绘簮鍩熷拰鍕曟厠(t脿i)鍔熻�楃鐞嗘鍒�锛屾湁鍔╀簬闄嶄綆鏁撮珨鍔熻�椼��
瑭茶姱鐗囬仼鐢ㄤ簬寤ｆ硾鐨勯牁鍩熷拰鎳夌敤鍫存櫙锛屽寘鎷絾涓嶉檺浜庯細
銆�銆�1. 宓屽叆寮忚瑕虹郴绲�(t菕ng)锛屽姗熷櫒瑕栬銆佸湒鍍忚檿鐞嗗拰瑕栭牷鍒嗘瀽銆�
銆�銆�2. 宸ユキ(y猫)鎺у埗鍜岃嚜鍕曞寲锛屼緥濡� PLC 鎺у埗鍣ㄣ�侀亱鍕曟帶鍒跺櫒鍜屾鍣ㄤ汉銆�
銆�銆�3. 閫氫俊鍩虹瑷柦锛屽灏忓瀷鍩虹珯銆佺劇绶氭帴鍏ョ恫(w菐ng)闂滃拰缍�(w菐ng)绲″姞閫熷崱銆�
銆�銆�4. 娑堣不椤為浕瀛�锛屼緥濡傞珮娓呴浕瑕�銆佹暩(sh霉)瀛椾俊铏熻檿鐞嗗櫒鍜屾櫤鑳藉灞呬腑妯炪��
銆�銆�5. 閱�(y墨)鐧傝ō鍌�锛屽瓒呰伈娉㈡垚鍍忓剙銆佺敓鍛介珨寰佺洠(ji膩n)娓剙绛�銆�
銆�銆�6. 姹借粖闆诲瓙锛屽 ADAS 杓斿姪椐曢绯荤当(t菕ng)鍜岃粖杓変俊鎭妯傜郴绲�(t菕ng)銆�
XC7Z100-FFG900C, XC7Z100-FFG900E
