鍨嬭櫉(h脿o)锛歑C7Z020
銆�銆�灏佽�濓細CLG400
銆�銆�閫熷害绛夌礆(j铆)锛�-2
銆�銆�FPGA閭忚集鍠�鍏冩��(sh霉)閲忥細绱�165,520鍊�(g猫)
銆�銆�鍏�(n猫i)缃甊AM瀹归噺锛氱磩2.2MB
銆�銆�DSP Slice鏁�(sh霉)閲忥細440鍊�(g猫)
銆�銆�閰嶇疆妯″紡锛氬緸Flash鍟熷嫊(d貌ng)鎴栭�氶亷(gu貌)JTAG瑾�(di脿o)瑭�
銆�銆�I/O Bank闆诲�撹寖鍦嶏��1.8V鑷�3.3V
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +85掳C

XC7Z020-2CLG400鐨勬牳蹇冪壒鎬у寘鎷�锛�
銆�銆�1. 闆嗘垚闆欐牳ARM Cortex-A9铏曠悊鍣�锛屼富闋绘渶楂樺彲閬�(d谩)667MHz锛屽叿鍌欐诞榛�(di菐n)閬�(y霉n)绠楀柈鍏冨拰NEON鍔犻�熷櫒銆�
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銆�銆�5. 鎻愪緵寮�(qi谩ng)澶х殑闁�(k膩i)鐧�(f膩)宸ュ叿閺�锛屽寘鎷琗ilinx Vivado Design Suite鍜孲DK锛屾柟渚跨敤鎴堕��(j矛n)琛岀‖浠惰ō(sh猫)瑷�(j矛)鍜岃粺浠剁法绋�銆�
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銆�銆�鍏稿瀷鐨勬噳(y墨ng)鐢ㄥ牬(ch菐ng)鏅�鍖呮嫭锛�
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銆�銆�5. 姹借粖闆诲瓙涓�鐨凙DAS锛堥珮绱�(j铆)椐曢�涜紨鍔╃郴绲�(t菕ng)锛夊拰淇℃伅濞涙▊(l猫)绯荤当(t菕ng)銆�

XC7Z010-2CLG400, XC7Z030-2FBG676