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闁辫畝锛�27
XC7VX980T-2FFG1926E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪楂樼 FPGA 鑺墖锛岄噰鐢� 28nm 宸ヨ棟鍒堕��銆傝┎鑺墖鍏锋湁楂樻�ц兘銆侀珮閭忚集瀵嗗害鍜岃睈瀵岀殑 I/O 鎺ュ彛锛岄仼鐢ㄤ簬寰╅洔淇¤櫉铏曠悊銆侀�氫俊绯荤当(t菕ng)銆佸湒鍍忚檿鐞嗕互鍙婇珮鎬ц兘瑷堢畻绛夋噳鐢ㄩ牁鍩�銆�
銆�銆�姝ゅ瀷铏熶腑鐨� XC 琛ㄧず Xilinx 鐨勭敘(ch菐n)鍝佺郴鍒�锛�7 琛ㄧず绗竷浠� Virtex 绯诲垪锛孷X980T 琛ㄧず鍏烽珨鐨� FPGA 鍣ㄤ欢椤炲瀷鍙婂閲�锛�-2 琛ㄧず閫熷害绛夌礆锛孎(xi脿n)FG1926 琛ㄧず灏佽褰㈠紡锛孍 琛ㄧず鍟嗙敤婧害鑼冨湇锛�0掳C 鑷� 85掳C锛夈��
閭忚集鍠厓锛�914,400
銆�銆�閰嶇疆瀛樺劜鍣細2.7 Mb
銆�銆�DSP Slice锛�3,240
銆�銆�Block RAM锛�52.4 Mb
銆�銆�I/O 鏁�(sh霉)閲忥細1,384
銆�銆�鏈�澶у伐浣滈牷鐜囷細550 MHz
銆�銆�渚涢浕闆诲锛�1.0V 鏍稿績闆诲 / 1.8V 杓斿姪闆诲
銆�銆�灏佽褰㈠紡锛欶FG1926
銆�銆�閫熷害绛夌礆锛�-2
XC7VX980T-2FFG1926E 鎻愪緵浜嗗挤澶х殑骞惰铏曠悊鑳藉姏鍜岄潏娲荤殑鍙法绋嬫��銆傚叾涓昏鐗规�у寘鎷細
銆�銆�1. 楂樻�ц兘鏋舵鏀寔楂橀仈 550 MHz 鐨勬檪閻橀牷鐜�锛屾豢瓒抽珮閫熸暩(sh霉)鎿�(j霉)鍌宠几闇�姹�銆�
銆�銆�2. 鍏�(n猫i)缃ぇ閲� DSP Slice锛岄仼鍚堢敤浜庡京闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�銆�
銆�銆�3. 鍖呭惈澶у閲� Block RAM 鍜屽垎甯冨紡 RAM锛岃兘澶犻珮鏁堢珐瀛樺拰绠＄悊鏁�(sh霉)鎿�(j霉)銆�
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銆�銆�5. 闆嗘垚浜嗙‖鏍歌檿鐞嗗櫒妯″锛堝闆嗘垚 ARM Cortex-A9 MPCore 铏曠悊鍣ㄧ殑鐗堟湰锛�锛屼究浜庡鐝�(xi脿n)宓屽叆寮忕郴绲�(t菕ng)瑷▓銆�
銆�銆�6. 鏀寔鍕曟厠(t脿i)閮ㄥ垎閲嶉厤缃姛鑳�锛屽厑瑷卞湪閬嬭鏅傞噸鏂板姞杓夐儴鍒嗛倧杓互鍎�(y艒u)鍖栬硣婧愬埄鐢�銆�
銆�銆�7. 鎻愪緵寤ｆ硾鐨勯枊鐧�(f膩)宸ュ叿鏀寔锛屽寘鎷� Vivado Design Suite锛屽公鍔╃敤鎴跺揩閫熷畬鎴愯ō瑷堟祦绋嬨��
瑭插瀷铏熷唬娉涙噳鐢ㄤ簬闇�瑕侀珮鎬ц兘瑷堢畻鑳藉姏鐨勫牬鏅�锛屽寘鎷絾涓嶉檺浜庯細
銆�銆�1. 鐒＄窔閫氫俊鍩虹珯瑷倷涓殑鍩哄付淇¤櫉铏曠悊銆�
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銆�銆�3. 閱�(y墨)鐧傚奖鍍忚ō鍌欎腑鐨勫鏅傚湒鍍忚檿鐞嗐��
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銆�銆�6. 瑕栭牷寤ｆ挱绯荤当(t菕ng)涓殑绶ㄧ⒓鑸囪В纰艰檿鐞�銆�
銆�銆�7. 鑸┖鑸ぉ闋樺煙鐨勫皫鑸垏鎺у埗绠楁硶瀵︾従(xi脿n)銆�
XC7VX980T-3FFG1926E
銆�銆�XC7VX1140T-2FFG1926E
