鏅傞枔锛�2025/5/7 17:48:49
闁辫畝锛�26
XC7VX980T-1FFG1926I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪楂樼 FPGA 鑺墖銆傝┎绯诲垪鑺墖閲囩敤 28nm 鍒堕�犲伐钘�锛屽叿鍌欓珮鎬ц兘銆侀珮瀵嗗害閭忚集鍠厓浠ュ強璞愬瘜鐨� DSP 鍜屽瓨鍎插櫒璩囨簮锛岄仼鐢ㄤ簬寰╅洔淇¤櫉铏曠悊銆佸祵鍏ュ紡瑕栬銆侀�氫俊绯荤当(t菕ng)瑷▓绛夊绋珮鎬ц兘瑷堢畻鍫存櫙銆�
銆�銆�Virtex-7 绯诲垪浠ュ叾瀵︾従楂橀�熶覆琛岄�ｆ帴鍜屽ぇ瀹归噺閭忚集璩囨簮鑰岃憲绋�锛屽唬娉涙噳鐢ㄤ簬闇�瑕侀珮鎬ц兘瑷堢畻鍜屽京闆滄暩鎿氳檿鐞嗙殑闋樺煙銆�
鍨嬭櫉锛歑C7VX980T-1FFG1926I
銆�銆�灏佽锛欶FG1926
銆�銆�I/O 鏁搁噺锛�1434
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏х疆闁冨瓨
銆�銆�宸ヤ綔婧害鑼冨湇锛氬伐妤�(y猫)绱氾紙-40掳C 鑷� +85掳C锛�
銆�銆�宸ヨ棟绡�(ji茅)榛烇細28nm
銆�銆�鍏ф牳闆诲锛�1.0V
銆�銆�杓稿叆杓稿嚭闆诲锛�1.8V/2.5V/3.3V
銆�銆�FPGA 瀹归噺锛�980K Logic Cells
銆�銆�RAM 璩囨簮锛�68Mb
銆�銆�DSP Slice 鏁搁噺锛�3240
銆�銆�鏈�澶у伐浣滈牷鐜囷細550MHz
銆�銆�鍔熻�楀吀鍨嬪�硷細绱�10W锛堣鍏烽珨鎳夌敤鑰屽畾锛�
XC7VX980T 鏄竴娆鹃珮搴﹂泦鎴愮殑 FPGA锛屽叾涓昏鐗归粸鍖呮嫭锛�
銆�銆�1. 楂樻�ц兘閭忚集绲愭锛氬熀浜� UltraScale 鏋舵鎶�琛�锛屾敮鎸侀珮鏁堢殑鏁告摎璺緫鍎�(y艒u)鍖栥��
銆�銆�2. 澶ц(gu墨)妯￠倧杓硣婧愶細鍖呭惈瓒呴亷 98 钀�嬮倧杓柈鍏�锛岃兘澶犲鐝惧京闆滅殑鏁稿瓧闆昏矾瑷▓銆�
銆�銆�3. 寮峰ぇ鐨� DSP 鏀寔锛氭搧鏈� 3240 鍊� DSP Slice锛屽彲婊胯冻楂樼簿搴︽诞榛為亱绠楀拰鐭╅櫍涔樻硶闇�姹傘��
銆�銆�4. 楂橀�熸敹鐧�(f膩)鍣細闆嗘垚澶氶仈 72 鍊� GTH/GTX 鏀剁櫦(f膩)鍣�锛屾渶楂樻敮鎸侀�熺巼鍙仈 13.1Gbps锛岄仼鍚堥珮閫熼�氫俊鎺ュ彛瑷▓銆�
銆�銆�5. 鍏х疆瀛樺劜鍣細鎻愪緵楂橀仈 68MB 鐨� Block RAM 鍜屽垎甯冨紡 RAM锛岀敤浜庢暩鎿氱珐娌栬垏鑷ㄦ檪瀛樺劜銆�
銆�銆�6. 闈堟椿鐨勬檪閻樼鐞嗭細鏀寔澶氳矾 PLL 鍜� MMCM 妯″锛岀偤瑷▓鎻愪緵绮剧⒑鐨勬檪閻樺垎閰嶅拰鐩镐綅瑾挎暣鍔熻兘銆�
銆�銆�7. 寤ｆ硾鐨勬噳鐢ㄥ牬鏅細寰炶埅绌鸿埅澶╁埌閱�(y墨)鐧傚奖鍍�锛屽啀鍒版暩鎿氫腑蹇冨姞閫�锛岃┎鍣ㄤ欢閮借兘鎻愪緵鍗撹秺鐨勬�ц兘琛ㄧ従銆�
XC7VX980T 涓昏鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 楂樻�ц兘瑷堢畻锛氫緥濡傞噾铻嶅缓妯�銆佸熀鍥犵祫鍒嗘瀽绛夐渶瑕佸ぇ閲忓苟琛岃▓绠楃殑浠诲嫏銆�
銆�銆�2. 宓屽叆寮忚瑕猴細鏀寔瀵︽檪鍦栧儚铏曠悊鍜岃闋绘祦鍒嗘瀽锛岄仼鐢ㄤ簬瀹夐槻鐩�(ji膩n)鎺у拰宸ユキ(y猫)鑷嫊鍖�銆�
銆�銆�3. 鏁告摎閫氫俊锛氬鐝鹃珮閫熺恫绲′氦鎻涙銆佽矾鐢卞櫒浠ュ強鐒＄窔鍩虹珯涓殑鍗旇瑙ｆ瀽鑸囨暩鎿氳綁鐧�(f膩)銆�
銆�銆�4. 閱�(y墨)鐧傝ō鍌欙細濡傝秴鑱叉尝鎴愬儚銆丆T 鎺冩弿鍎�绛夊皪寤堕伈鏁忔劅涓旇▓绠楀瘑闆嗗瀷鐨勯啱(y墨)鐧傝ê鏂峰剙鍣�銆�
銆�銆�5. 宸ユキ(y猫)鎺у埗锛氬埄鐢ㄥ叾璞愬瘜鐨勫瑷帴鍙ｅ拰寮峰ぇ鐨勮檿鐞嗚兘鍔�锛屽煼(zh铆)琛屽京闆滅殑閬嬪嫊鎺у埗绠楁硶銆�
XC7VX690T-1FFG1926I
銆�銆�XC7VX1140T-1FFG1926I
