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XC7VX690T-L2FFG1926E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪楂樼 FPGA 鑺墖锛屽熀浜� 28nm 鍒剁▼宸ヨ棟瑷▓銆傝┎绯诲垪 FPGA 闈㈠悜楂樻�ц兘瑷堢畻銆侀�氫俊绯荤当(t菕ng)銆佽闋昏檿鐞嗗拰淇¤櫉铏曠悊绛夋噳鐢ㄩ牁鍩�锛屾彁渚涢珮閭忚集瀵嗗害銆侀珮閫熶覆琛岄�ｆ帴鑳藉姏鍜岃睈瀵岀殑 DSP 璩囨簮銆�
銆�銆�XC7VX690T 鏄┎绯诲垪涓殑涓�娆鹃珮瀹归噺鍨嬭櫉锛屾敮鎸佸閬� 690K 閭忚集鍠厓锛屽叿鏈夊嚭鑹茬殑鎬ц兘鍜岄潏娲绘�с�傚叾 L2 琛ㄧず閫熷害绛夌礆锛孎(xi脿n)FG1926E 鏄皝瑁濋鍨嬨��
鍨嬭櫉锛歑C7VX690T-L2FFG1926E
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歏irtex-7
銆�銆�鍒剁▼宸ヨ棟锛�28nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細690K
銆�銆�RAM 瀹归噺锛氱磩 35.4Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細3,990
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細鏈�澶� 1,152
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster SPI銆丼lave SPI
銆�銆�宸ヤ綔闆诲锛氭牳蹇冮浕澹� 1.0V锛孖/O 闆诲 1.8V/2.5V/3.3V
銆�銆�灏佽锛欶FG1926E
銆�銆�閫熷害绛夌礆锛歀2
1. 楂樻�ц兘鏋舵锛氶噰鐢� UltraScale 鏋舵锛屾敮鎸侀珮閬� 690K 鐨勯倧杓柈鍏�锛屾豢瓒冲京闆滆ō瑷堥渶姹傘��
銆�銆�2. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細闆嗘垚 24 鍊� GTX 鏀剁櫦(f膩)鍣�锛岄�熺巼鑼冨湇鐐� 1Gbps 鑷� 11.25Gbps锛岄仼鐢ㄤ簬楂橀�熼�氫俊鎺ュ彛銆�
銆�銆�3. DSP 鍔熻兘寮峰ぇ锛氬収(n猫i)宓� 3,990 鍊� DSP Slice锛屾敮鎸侀珮鏁堟诞榛為亱绠楀拰瀹氶粸閬嬬畻锛岄仼鐢ㄤ簬鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�銆�
銆�銆�4. 鍏�(n猫i)缃瓨鍎茶硣婧愶細鎿佹湁绱� 35.4Mb 鐨勫垎甯冨紡 RAM 鍜屽鐙� RAM锛岄仼鍚堟暩(sh霉)鎿�(j霉)绶╁瓨鍜屾煡鎵捐〃瀵︾従(xi脿n)銆�
銆�銆�5. 澶氱ó I/O 妯欐簴鏀寔锛氬吋瀹瑰绋富娴佹婧�锛屽 LVDS銆丠STL銆丼STL 绛�锛屾柟渚胯垏澶栭儴瑷倷浜掕伅(li谩n)銆�
銆�銆�6. 閰嶇疆闈堟椿锛氭敮鎸佸绋厤缃ā寮�锛屽寘鎷� SelectMAP 鍜� SPI 鎺ュ彛锛屼究浜庡揩閫熷暉鍕曞拰鏇存柊鍥轰欢銆�
銆�銆�7. 浣庡姛鑰楄ō瑷堬細閫氶亷鍕曟厠(t脿i)闆绘簮绠＄悊鍜屾檪閻橀杸鎺ф妧琛撻檷浣庨亱琛屽姛鑰�銆�
1. 楂樻�ц兘瑷堢畻锛氱敤浜庢暩(sh霉)鎿�(j霉)涓績鍔犻�熷崱銆佷汉宸ユ櫤鑳芥帹鐞嗗紩鎿庣瓑鍫存櫙銆�
銆�銆�2. 閫氫俊绯荤当(t菕ng)锛氶仼鍚堜綔鐐哄熀甯惰檿鐞嗗柈鍏�銆佷氦鎻涚煩闄ｆ帶鍒跺櫒鎴栫恫(w菐ng)绲¤檿鐞嗗櫒銆�
銆�銆�3. 瑕栭牷铏曠悊锛氬彲鎳夌敤浜庡鏅傚湒鍍忚檿鐞�銆佽闋荤法纰艰В纰间互鍙婂濯掗珨娴佺檪鎴愬儚锛氭敮鎸佽秴鑱叉尝銆丆T 鎺冩弿绛夐啱(y墨)鐧傝ō鍌欎腑鐨勪俊铏熼噰闆嗚垏铏曠悊銆�
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ綔閬嬪嫊鎺у埗鍣�銆丳LC 绶ㄧ▼鏍稿績鎴栨櫤鑳藉偝鎰熷櫒鐨勪富鎺ц姱鐗囥��
銆�銆�6. 姹借粖闆诲瓙锛氭豢瓒宠粖杓変俊鎭妯傜郴绲�(t菕ng)銆侀珮绱氶椐涜紨鍔╃郴绲�(t菕ng)鐨勯珮鎬ц兘闇�姹�銆�
XC7VX690T-L3FFG1926E
銆�銆�XC7VX690T-3FFG1926E
銆�銆�XC7VX690T-2FFG1926E
