鏅傞枔锛�2025/5/16 18:59:29
闁辫畝锛�24
XC7VX485T-3FFG1927I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪楂樼 FPGA 鑺墖銆傝┎绯诲垪涓昏闈㈠悜楂樻�ц兘瑷堢畻銆佷俊铏熻檿鐞�銆侀�氫俊绯荤当(t菕ng)浠ュ強鑸┖鑸ぉ绛夊京闆滄噳鐢ㄩ牁鍩�锛屽叿鏈夎睈瀵岀殑閭忚集璩囨簮鍜岄珮閫熶覆琛屾帴鍙ｈ兘鍔涖��
銆�銆�姝ゅ瀷铏熶腑鐨勫叿楂斿弮鏁�(sh霉)鍚京鐐猴細XC 琛ㄧず Xilinx 鐨勭敘(ch菐n)鍝佺窔锛�7 琛ㄧず绗竷浠� Virtex 绯诲垪锛孷X 琛ㄧず Virtex-7 绯诲垪涓殑楂樻�ц兘瀛愮郴鍒�锛�485 琛ㄧず FPGA 鍏ч儴鍖呭惈鐨勯倧杓柈鍏冩暩(sh霉)閲忥紙绱� 485K锛�锛孴 琛ㄧず閫熷害绛夌礆锛�-3 琛ㄧず鍟嗙敤婧害鑼冨湇涓嬬殑閫熷害绛夌礆锛�锛孎(xi脿n)FG1927 琛ㄧず灏佽椤炲瀷锛孖 琛ㄧず宸ユキ(y猫)绱氬伐浣滄韩搴﹁寖鍦嶏紙-40掳C 鑷� +100掳C锛�銆�
閭忚集鍠厓鏁�(sh霉)锛�485K
銆�銆�閰嶇疆瀛樺劜鍣細22 Mbits
銆�銆�RAM 璩囨簮锛�28.8 Mbits
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2940
銆�銆�鏈�澶х敤鎴� I/O锛�860
銆�銆�鏅傞悩绠＄悊鍠厓锛�
銆�銆�PCIE 妯″锛氬閬� 4 鍊� Gen3 x8 鏀寔
銆�銆�DDR 鎺ュ彛鏀寔锛欴DR3/DDR2/LPDDR2
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�灏佽椤炲瀷锛欶FG1927
銆�銆�閫熷害绛夌礆锛�-3
XC7VX485T-3FFG1927I 鎻愪緵浜嗗挤澶х殑閭忚集鍜屼俊铏熻檿鐞嗚兘鍔�锛岄仼鐢ㄤ簬楂樻�ц兘瑷堢畻鍜屽京闆滃祵鍏ュ紡绯荤当(t菕ng)銆�
銆�銆�鍏堕棞閸电壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘 DSP Slice锛氭瘡鍊� DSP Slice 鍖呭惈 27x18 浣嶄箻娉曞櫒鍜岀疮鍔犲櫒锛屾敮鎸侀珮绮惧害娴粸閬嬬畻鍜屾烤娉㈠櫒瑷▓銆�
銆�銆�2. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細闆嗘垚楂橀仈 13.1 Gbps 鐨� GTX/GTH 鏀剁櫦(f膩)鍣�锛屽彲闈堟椿鏀寔澶氱ó鍗�(xi茅)璀帮紙濡� PCIe Gen3銆丆PRI銆丼RIO 鍜� 10GbE锛�銆�
銆�銆�3. 澶у閲� Block RAM 鍜屽垎甯冨紡 RAM锛氭彁渚涚附瑷� 28.8 Mbits 鐨勫瓨鍎茶硣婧愶紝閬╁悎鏁�(sh霉)鎿�(j霉)绶╁瓨鍜� FIFO 瑷▓銆�
銆�銆�4. 鍙法绋嬫檪閻樼恫(w菐ng)绲★細閰嶅倷 8 鍊� MMCM锛堝妯℃檪閻樼鐞嗘ā濉婏級鍜� PLL锛屾敮鎸佸京闆滅殑鏅傞悩鍒嗛牷鑸囧悓姝ユ搷浣�銆�
銆�銆�5. 楂橀�熷瑷帴鍙ｏ細鏀寔 DDR3/DDR2/LPDDR2 瀛樺劜鍣ㄦ帴鍙ｏ紝閫熺巼鍙仈 1600 Mbps锛屽悓鏅傚叿鍌欑‖鏍镐笁妯� PCIE 妯″銆�
銆�銆�6. 楂樺彲闈犳�цō瑷堬細绗﹀悎鑸ぉ鑸囧湅闃茶妤�(y猫)鐨勬姉杓诲皠闇�姹�锛岄仼鐢ㄤ簬妤电鐠�(hu谩n)澧�銆�
XC7VX485T-3FFG1927I 寤ｆ硾鎳夌敤浜庨渶瑕侀珮鍚炲悙閲忓拰浣庡欢閬茬殑鍫存櫙锛屼緥濡傦細
銆�銆�1. 閫氫俊鍩虹瑷柦锛氱劇绶氬熀绔�銆佹牳蹇冭矾鐢卞櫒鍜屼氦鎻涙涓殑鏁�(sh霉)鎿�(j霉)鍖呰檿鐞嗐��
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細瀵︽檪瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佽▓绠楁瑕栬绠楁硶鍔犻��銆�
銆�銆�3. 楂樻�ц兘瑷堢畻锛氱瀛歌▓绠�銆侀噾铻嶅缓妯°�佸姞瀵嗚В瀵嗙畻娉曞鐝�(xi脿n)銆�
銆�銆�4. 閱�(y墨)鐧傛垚鍍忥細瓒呰伈娉��丆T 鎺冩弿绛夎ō鍌欎腑鐨勬暩(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞�銆�
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栵細閬嬪嫊鎺у埗銆佹鍣ㄤ汉瑕栬鍜屽鏅傜洠(ji膩n)鎺х郴绲�(t菕ng)銆�
銆�銆�6. 鑸┖鑸ぉ鑸囧湅闃诧細琛�(w猫i)鏄熼�氫俊銆侀浄閬斾俊铏熻檿鐞嗗強灏庤埅绯荤当(t菕ng)銆�
XC7VX485T-2FFG1927C, XC7VX485T-3FFG1156I
