鏅傞枔锛�2025/4/30 17:57:19
闁辫畝锛�24
XC7VH870T-2FLG1932 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪楂樼 FPGA 鑺墖锛屽皥鐐洪珮鎬ц兘瑷堢畻銆侀�氫俊銆佸唬鎾闋昏檿鐞嗗拰楂樼礆娓│瑷倷绛夋噳鐢ㄨō瑷�銆傝┎鍣ㄤ欢閲囩敤 28nm 鍒剁▼宸ヨ棟鍒堕��锛屽叿鍌欓珮閭忚集瀵嗗害銆侀珮閫熶覆琛岄�ｆ帴鑳藉姏鍜岃睈瀵岀殑 DSP 妯″璩囨簮銆傚畠鏀寔楂橀仈 896 鍊嬫暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) Slice 鍜岃秴閬� 50 钀�嬮倧杓柈鍏�锛岃兘澶犳豢瓒冲京闆滅畻娉曠殑纭欢鍔犻�熼渶姹�銆�
銆�銆�姝ゅ锛孹C7VH870T 閰嶅倷浜嗗ぇ瀹归噺 Block RAM 鍜屽垎甯冨紡瀛樺劜鍣ㄨ硣婧�锛屽苟闆嗘垚浜嗗鍊嬮珮閫熸敹鐧�(f膩)鍣� (GTX/GTH)锛屽彲瀵︾従(xi脿n)楂橀仈 13.1 Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼銆�
鍨嬭櫉锛歑C7VH870T-2FLG1932
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歏irtex-7
銆�銆�灏佽椤炲瀷锛欶G1932
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細541920
銆�銆�DSP Slice 鏁�(sh霉)閲忥細896
銆�銆�RAM 瀹归噺锛氱磩 37.5MB (鍖呮嫭 Block RAM 鍜屽垎甯冨紡 RAM)
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄦ暩(sh霉)閲忥細鏈�澶� 48 鍊�
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼锛氭渶楂� 13.1 Gbps
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細1864
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�鍒剁▼宸ヨ棟锛�28nm
銆�銆�闆绘簮闆诲锛氬鏍镐緵闆伙紙鍏烽珨鍊肩敱瑷▓姹哄畾锛�
XC7VH870T 鎻愪緵鍗撹秺鐨勬�ц兘鍜岄潏娲绘��锛屽叾涓昏鐗归粸濡備笅锛�
銆�銆�1. 鍩轰簬 28nm 宸ヨ棟鎶�琛擄紝鎻愪緵鏇撮珮鐨勯泦鎴愬害鍜屾洿浣庣殑鍔熻��銆�
銆�銆�2. 鍏�(n猫i)缃睈瀵岀殑 DSP Slice锛岄仼鍚堢敤浜庢诞榛為亱绠�銆佹烤娉㈠櫒鍜屽叾浠栨暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�銆�
銆�銆�3. 鏀寔澶氱ó宓屽叆寮忓瓨鍎插櫒閬搁爡锛屽 Block RAM銆佸垎甯冨紡 RAM 鍜� FIFO銆�
銆�銆�4. 鎻愪緵闈堟椿鐨勬檪閻樼鐞嗗伐鍏� (Clock Management Tile)锛屽寘鎷� PLL 鍜� MMCM锛屼互鍎�(y艒u)鍖栫郴绲�(t菕ng)鏅傞悩鍒嗛厤銆�
銆�銆�5. 鍖呭惈澶氶仈 48 鍊嬮珮閫熶覆琛屾敹鐧�(f膩)鍣�锛屾敮鎸佸緸 PCIe Gen3 鍒� CPRI/LTE 绛夊绋�氫俊鍗�(xi茅)璀�銆�
銆�銆�6. 鏀寔 AXI4 鎺ュ彛妯欐簴锛屼究浜庤垏澶栭儴铏曠悊鍣ㄦ垨瀛樺劜鍣ㄩ�茶楂樻晥鏁�(sh霉)鎿�(j霉)浜や簰銆�
銆�銆�7. 鍙�氶亷 Vivado 瑷▓濂椾欢瀹屾垚蹇�熼枊鐧�(f膩)鍜岄璀�锛岀啊鍖栫敤鎴剁殑瑷▓娴佺▼銆�
銆�銆�8. 鍏�(n猫i)缃� PowerPC 440 铏曠悊鍣ㄧ‖鏍革紙閮ㄥ垎閰嶇疆鏀寔锛�锛岄�蹭竴姝ユ摯灞曚簡绯荤当(t菕ng)鐨勫姛鑳借寖鍦�銆�
XC7VH870T 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 楂樻�ц兘瑷堢畻 (HPC)锛屼緥濡傜煩闄ｉ亱绠�銆佺瀛镐豢鐪熺瓑銆�
銆�銆�2. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�熷崱锛岀敤浜庣恫(w菐ng)绲″寘铏曠悊鎴栨暩(sh霉)鎿�(j霉)搴煡瑭㈠劒(y艒u)鍖�銆�
銆�銆�3. 閫氫俊鍩虹瑷柦锛屽鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鏍稿績铏曠悊妯″銆�
銆�銆�4. 瑕栭牷寤ｆ挱瑷倷锛屾敮鎸侀珮娓�/瓒呴珮娓呭鏅傜法纰艰В纰煎強鍦栧儚铏曠悊銆�
銆�銆�5. 娓│娓噺鍎�鍣�锛屼緥濡傜ず娉㈠櫒銆佷俊铏熺櫦(f膩)鐢熷櫒鍜屽崝(xi茅)璀板垎鏋愬剙銆�
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栨帶鍒�锛屾秹鍙婂京闆滅殑閬嬪嫊鎺у埗鍜屾暩(sh霉)鎿�(j霉)閲囬泦浠诲嫏銆�
銆�銆�7. 閱�(y墨)鐧傚奖鍍忚ō鍌�锛屽 CT 鎺冩弿鍎�鍜岃秴鑱叉尝瑷烘柗鍎�鐨勬暩(sh霉)鎿�(j霉)铏曠悊鍠厓銆�
XC7VX690T-2FFG1930, XC7VH580T-2FFG1157
