鍨嬭櫉(h脿o)锛歑C7S25-1CSGA225Q
銆�銆�绯诲垪锛欰rtix-7
銆�銆�鍝佺墝锛歑ilinx
銆�銆�宸ヨ棟绡�(ji茅)榛�(di菐n)锛�28nm
銆�銆�FPGA閭忚集鍠�鍏冩��(sh霉)閲忥細绱�25K
銆�銆�RAM澶у皬锛�1.3Mb
銆�銆�DSP Slice鏁�(sh霉)閲忥細64
銆�銆�I/O寮曡叧鏁�(sh霉)閲忥細170
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster/Slave SPI銆丅PI
銆�銆�渚涢浕闆诲�擄細Vccint=0.9V, Vccaux=1.8V, Vccbram=1.0V, Vccio=1.2V/1.5V/1.8V/2.5V/3.3V
銆�銆�灏佽�濋�炲瀷锛欳SGA锛圕eramic Solder Grid Array锛�
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +85掳C
銆�銆�閫熷害绛夌礆(j铆)锛�-1

XC7S25-1CSGA225Q 鎻愪緵浜嗗挤(qi谩ng)澶х殑鍔熻兘鍜屽劒(y艒u)鍖栫殑鎬ц兘鐗归粸(di菐n)锛屼互涓嬫槸鍏朵富瑕佺壒鎬э細
銆�銆�1. 楂樻�ц兘鑸囦綆鍔熻�楋細Artix-7 绯诲垪閲囩敤浜嗙崹(d煤)鐗圭殑 UltraScale 鏋舵��(g貌u)鍜� Power Matters Alliance 鎶�琛�(sh霉)锛岃兘澶犲湪淇濊瓑鎬ц兘鐨勫悓鏅�(sh铆)澶у箙闄嶄綆鍔熻��銆�
銆�銆�2. 澶氱ó纭�浠惰硣婧愶細鍖呮�� 25K 鐨勯倧杓�鍠�鍏冿紙CLBs锛夈��64 鍊�(g猫) DSP48E1 Slice銆丅lock RAM 鍜屽垎甯冨紡 RAM锛屾豢瓒冲京(f霉)闆滅畻娉曞��(sh铆)鐝�(xi脿n)鐨勯渶姹�銆�
銆�銆�3. 楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛氶洊鐒舵�ゅ瀷铏�(h脿o)鏈�闆嗘垚楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛屼絾鏀�鎸侀�氶亷(gu貌)澶栭儴 PHY 鑺�鐗囧��(sh铆)鐝�(xi脿n)楂橀�熼�氫俊鎺ュ彛銆�
銆�銆�4. 寮�(qi谩ng)澶х殑鏅�(sh铆)閻樼�＄悊锛氶泦鎴愪�� PLL 鍜� MMCM锛堟贩鍚堟ā寮忔檪(sh铆)閻樼�＄悊鍣�锛�锛屽彲鐢熸垚绮剧⒑鐨勬檪(sh铆)閻橀牷鐜囧苟閫�(j矛n)琛岀浉浣嶈��(di脿o)鏁淬��
銆�銆�5. 寤ｆ硾鐨� I/O 鏀�鎸侊細鏀�鎸佸�氱ó妯�(bi膩o)婧�(zh菙n) I/O 鍗�(xi茅)璀�锛屽�� LVDS銆丠STL銆丼STL 绛�锛屽苟鍏煎�瑰�氱ó闆诲�撻浕骞�銆�
銆�銆�6. 鍙�闈犳�ч珮锛氬叿鍌� ECC 鍏�(n猫i)瀛樹繚璀�(h霉)姗�(j墨)鍒�锛屾彁楂樹簡绯荤当(t菕ng)鐨勫彲闈犳�с��
銆�銆�7. 鏄撶敤鐨勯枊(k膩i)鐧�(f膩)宸ュ叿锛氫娇鐢� Vivado Design Suite 鎴� ISE Design Suite 閫�(j矛n)琛岃ō(sh猫)瑷�(j矛)闁�(k膩i)鐧�(f膩)锛屾彁渚涗簡寰炰豢鐪熷埌缍滃悎鍐嶅埌瀵�(sh铆)鐝�(xi脿n)鐨勪竴绔欏紡瑙ｆ焙鏂规��銆�
銆�銆�8. 灏佽�濆皬宸э細閲囩�� CSGA225 灏佽��锛屽昂瀵哥穵婀�锛岄仼鍚堝皪(du矛)绌洪枔瑕佹眰杓冮珮鐨勬噳(y墨ng)鐢ㄥ牬(ch菐ng)鏅�銆�

XC7S25-1CSGA225Q 涓昏�侀仼鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 宓屽叆寮忚�栬��(ju茅)绯荤当(t菕ng)锛氫緥濡傝�栭牷鐩�(ji膩n)鎺�銆佸湒鍍忚檿鐞嗐�佹��(j墨)鍣ㄨ�栬��(ju茅)绛�銆�
銆�銆�2. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栵細鍖呮嫭閬�(y霉n)鍕�(d貌ng)鎺у埗銆佸��(sh铆)鏅�(sh铆)鏁�(sh霉)鎿�(j霉)閲囬泦銆佹��(j墨)鍣ㄤ汉鎺у埗绛�銆�
銆�銆�3. 閱�(y墨)鐧傞浕瀛愯ō(sh猫)鍌欙細濡傝秴鑱叉尝鎴愬儚銆佹偅鑰呯洠(ji膩n)璀�(h霉)鍎�銆佷究鏀滃紡瑷烘柗鍎�鍣ㄧ瓑銆�
銆�銆�4. 閫氫俊鍩虹��(ch菙)瑷�(sh猫)鏂斤細鐢ㄤ簬灏忓瀷鍩虹珯銆佺劇(w煤)绶氫腑绻煎櫒銆佺恫(w菐ng)绲�(lu貌)鎺ュ彛鍗＄瓑銆�
銆�銆�5. 娑堣不(f猫i)椤為浕瀛愮敘(ch菐n)鍝侊細娓告埐姗�(j墨)銆佸�氬獟楂旀挱鏀惧櫒銆佹櫤鑳藉�堕浕涓�鐨勬暩(sh霉)鎿�(j霉)铏曠悊妯″��銆�
銆�銆�6. 鑸�绌鸿埅澶╄垏鍦�(gu贸)闃诧細闆烽仈(d谩)绯荤当(t菕ng)銆佽��(w猫i)鏄熼�氫俊銆佸皫(d菐o)鑸�鎺у埗绛夊��(du矛)鍙�闈犳�ц�佹眰妤甸珮鐨勫��(ch菐ng)鍚�銆�

XC7S25-2CSGA225Q
銆�銆�XC7S25-3CSGA225Q