閭忚集鍠�鍏冩��(sh霉)閲忥細70K
銆�銆�閰嶇疆瀛樺劜(ch菙)鍣�锛�1.4Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細440
銆�銆�Block RAM 鏁�(sh霉)閲忥細350Kb
銆�銆�IO 寮曡叧鏁�(sh霉)锛�504
銆�銆�鏈�澶у伐浣滈牷鐜囷細550MHz
銆�銆�鍒剁▼宸ヨ棟锛�28nm
銆�銆�灏佽�濋�炲瀷锛欶BGA676
銆�銆�渚涢浕闆诲�擄��1.0V 鏍稿績闆诲�擄��1.8V 杓斿姪闆诲��
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��0掳C 鑷� 85掳C

XC7K70T-1FBG676I 鐨勪富瑕佺壒鎬у寘鎷�锛�
銆�銆�1. 楂樻�ц兘鏋舵��(g貌u)锛氶噰鐢� UltraScale 鏋舵��(g貌u)鍓嶇殑楂樼礆(j铆)浜掕伅(li谩n)鎶�琛�(sh霉)锛屾彁渚涙洿蹇�鐨勬��(sh霉)鎿�(j霉)鍚炲悙鐜囥��
銆�銆�2. 鍏�(n猫i)缃�纭�鏍告ā濉婏細鏀�鎸� PCIe Gen2 x8 纭�鏍告ā濉�锛岄仼鍚堥珮閫熸暩(sh霉)鎿�(j霉)鍌宠几鎳�(y墨ng)鐢ㄣ��
銆�銆�3. 璞愬瘜鐨勫�栬��(sh猫)鎺ュ彛锛氬寘鎷� Gigabit Transceivers锛堟渶楂樻敮鎸� 6.6Gbps 鏁�(sh霉)鎿�(j霉)閫熺巼锛夊拰闈堟椿鐨� IO Bank 閰嶇疆銆�
銆�銆�4. 鍔熻�楀劒(y艒u)鍖栵細閫氶亷(gu貌)鍕�(d貌ng)鎱�(t脿i)鍔熻�楃�＄悊鎶�琛�(sh霉)鍜岀墖涓婇浕婧愮洠(ji膩n)鎺у姛鑳�锛岄檷浣庣郴绲�(t菕ng)鏁撮珨鍔熻�椼��
銆�銆�5. 鍙�闈犳�у�炲��(qi谩ng)锛氬叿鍌欏柈浜嬩欢缈昏綁(zhu菐n) (SEU) 妾㈡脯(c猫)鑸囩尘姝ｆ��(j墨)鍒�锛屾彁鍗囧湪鎯″姡鐠�(hu谩n)澧冧笅鐨勯亱(y霉n)琛岀┅(w臎n)瀹氭��銆�
銆�銆�6. 闁�(k膩i)鐧�(f膩)宸ュ叿鏀�鎸侊細Xilinx Vivado Design Suite 鎻愪緵鍏ㄩ潰鐨勮ō(sh猫)瑷�(j矛)銆佷豢鐪熷拰椹�(y脿n)璀夌挵(hu谩n)澧�銆�

XC7K70T-1FBG676I 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊瑷�(sh猫)鍌欙細濡傜劇(w煤)绶氬熀绔�銆佺恫(w菐ng)绲�(lu貌)浜ゆ彌姗�(j墨)绛夐渶瑕侀珮甯跺��铏曠悊鑳藉姏鐨勫牬(ch菐ng)鏅�銆�
銆�銆�2. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栵細鐢ㄤ簬瀵�(sh铆)鏅�(sh铆)鎺у埗銆佸湒鍍忚檿鐞嗕互鍙婃��(j墨)鍣ㄤ汉瑕栬��(ju茅)绯荤当(t菕ng)銆�
銆�銆�3. 閱�(y墨)鐧傝ō(sh猫)鍌欙細鏀�鎸佽秴鑱叉尝鎴愬��銆丆T 鎺冩弿鍎�绛夐珮鎬ц兘瑷�(j矛)绠椾换鍕�(w霉)銆�
銆�銆�4. 娓�(c猫)瑭︽脯(c猫)閲�?j墨)x鍣�锛氫緥濡備俊铏�(h脿o)鍒嗘瀽鍎�銆侀牷璀滃垎鏋愬剙绛夐渶瑕佸揩閫熸暩(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞嗙殑鎳�(y墨ng)鐢ㄣ��
銆�銆�5. 瑕栭牷鑸囧唬鎾�锛氱敤浜庤�栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓�炲��(qi谩ng)浠ュ強澶氳矾瑕栭牷娴佽檿鐞�銆�

XC7K70TFBG676-1
銆�銆�XC7K70TFFG676-1
銆�銆�XC7K70TFFG484-1