閭忚集鍠�鍏冿��483,480
銆�銆�鏌ユ壘琛� (LUTs)锛�290,400
銆�銆�瀵勫瓨鍣�锛�580,800
銆�銆�DSP Slice锛�2,320
銆�銆�Block RAM锛�2,272 Kb
銆�銆�閰嶇疆闁冨瓨锛氱劇鐗囦笂闁冨瓨
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�840
銆�銆�鏀�鎸佺殑鏈�澶х敤鎴� I/O锛�720
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�灏佽�濋�炲瀷锛欶FG1156 (1156 寮曡叧)

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銆�銆�3. 澶у�归�� Block RAM锛氭彁渚涢珮閬�(d谩) 2,272 Kb 鐨勫垎甯冨紡瀛樺劜鍣ㄥ拰濉婂瓨鍎插櫒锛岄仼鍚堟暩(sh霉)鎿�(j霉)绶╂矕銆佹煡鎵捐〃浠ュ強鍏朵粬瀛樺劜闇�姹傘��
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銆�銆�5. 鍔熻�楀劒(y艒u)鍖栵細閲囩敤 Xilinx 鐨� Vivado Design Suite 宸ュ叿锛屽彲浠ュ皪瑷�(sh猫)瑷堥��(j矛n)琛屽姛鑰楀劒(y艒u)鍖�锛岄檷浣庢暣楂旈亱琛岃兘鑰�銆�
銆�銆�6. 鏀�鎸佸�氱ó閰嶇疆妯″紡锛氬彲閫氶亷 JTAG銆丼electMAP銆丮aster SPI 鍜� Slave SPI 绛夋柟寮忛��(j矛n)琛岄潏娲荤殑 FPGA 閰嶇疆銆�
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XC7K480T-3FFG1156C
銆�銆�XC7K410T-2FFG1156C
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