鍨嬭櫉锛歑C7K420T-L2FFG901E
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛欰rtix-7
銆�銆�灏佽�濋�炲瀷锛欶FG901
銆�銆�I/O 鏁�(sh霉)閲忥細532
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)閮ㄩ杻瀛�
銆�銆�鏈�澶х敤鎴跺彲鐢ㄩ倧杓�鍠�鍏冿細420,000
銆�銆�Block RAM 瀹归噺锛氱磩 27 Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細1,080
銆�銆�鏅傞悩璩囨簮锛氭渶澶氭敮鎸� 16 鍊� PLL
銆�銆�鏈�灏忓伐浣滄韩搴︼細-40掳C
銆�銆�鏈�澶у伐浣滄韩搴︼細+100掳C
銆�銆�渚涢浕闆诲�擄��0.9V 鏍稿績闆诲�擄��1.0V 杓斿姪闆绘簮

XC7K420T-L2FFG901E 鎻愪緵浜嗗挤澶х殑鍙�绶ㄧ▼閭忚集璩囨簮鍜岄潏娲荤殑浜掗�ｆ灦妲�(g貌u)锛屼娇鍏堕仼鐢ㄤ簬澶氱ó寰�(f霉)闆滅殑瑷�(sh猫)瑷堥渶姹�銆�
銆�銆�1. 鍩轰簬 UltraScale 鏋舵��(g貌u)鐨勬敼閫茬増鏈�锛屽叿鏈夋洿楂樼殑閬嬭�屾晥鐜囧拰鏇翠綆鐨勫姛鑰�銆�
銆�銆�2. 鍏�(n猫i)缃�璞愬瘜鐨� DSP Slice 鍜� Block RAM锛岃兘澶犳敮鎸佸京(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗗拰绠楁硶瀵︾従(xi脿n)銆�
銆�銆�3. 鏀�鎸佸�氱ó楂橀�熶覆琛屾帴鍙�锛屼緥濡� GTX 鏀剁櫦(f膩)鍣�锛岄�熺巼楂橀仈 6.6 Gbps锛屾豢瓒崇従(xi脿n)浠ｉ�氫俊绯荤当(t菕ng)鐨勮�佹��銆�
銆�銆�4. 鎻愪緵闈堟椿鐨勬檪閻樼�＄悊宸ュ叿锛圕lock Management Tile锛�锛屾敮鎸� PLL 鍜� MMCM 妯″�婁互鍎�(y艒u)鍖栨檪閻樺垎閰嶃��
銆�銆�5. 鍖呭惈纭�鏍� PCIe Gen2 鍗�(xi茅)璀版帶鍒跺櫒锛屾柟渚胯垏涓绘�熸垨鍏朵粬澶栬��(sh猫)閫茶�岄珮閫熼�氫俊銆�
銆�銆�6. FPGA 鐨勮ō(sh猫)瑷堟祦绋嬪彲浠ュ�熷姪 Vivado Design Suite 鎴� ISE Design Suite 瀹屾垚锛岀啊鍖栭枊鐧�(f膩)鍛ㄦ湡銆�
銆�銆�7. 宸ユキ(y猫)绱氭韩搴﹁寖鍦嶏紙-40掳C 鑷� +100掳C锛変繚璀変簡鍦ㄦサ绔�鐠�(hu谩n)澧冧笅鐨勫彲闈犳��銆�

XC7K420T-L2FFG901E 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬闇�瑕侀珮鎬ц兘鍜屼綆鍔熻�楃殑鍫存櫙锛屽寘鎷�浣嗕笉闄愪簬锛�
銆�銆�1. 宸ユキ(y猫)鑷�鍕曞寲锛氬�︽檪鎺у埗銆侀亱鍕曟帶鍒跺拰鏁�(sh霉)鎿�(j霉)閲囬泦銆�
銆�銆�2. 閫氫俊鍩虹��(ch菙)瑷�(sh猫)鏂斤細鐒＄窔鍩虹珯銆佸皬鍨嬭渹绐╃恫(w菐ng)闂�(gu膩n)銆佷俊铏熻��(di脿o)鍒惰В瑾�(di脿o)绛夈��
銆�銆�3. 閱�(y墨)鐧傛垚鍍忥細瓒呰伈娉㈣檿鐞嗗櫒銆丆T 鍦栧儚閲嶅缓銆�
銆�銆�4. 瑕栭牷铏曠悊锛氶珮娓呰�栭牷绶ㄧ��/瑙ｇ⒓銆佸湒鍍忓�炲��銆�
銆�銆�5. 鏁�(sh霉)鎿�(j霉)涓�蹇冨姞閫燂細姗熷櫒瀛�(xu茅)缈�(x铆)鎺ㄧ悊銆佹暩(sh霉)鎿�(j霉)搴�鏌ヨ�㈠姞閫熴��
銆�銆�6. 姹借粖闆诲瓙锛氶珮绱氶�曢�涜紨鍔╃郴绲�(t菕ng)锛圓DAS锛�銆佽粖杓変俊鎭�濞涙▊绯荤��(t菕ng)銆�
銆�銆�7. 娓�瑭︽脯閲忥細绀烘尝鍣ㄨЦ鐧�(f膩)妯″��銆佸崝(xi茅)璀板垎鏋愬剙銆�

XC7K410T-2FFG901I, XC7K420T-2FFG676I