閭忚集鍠�鍏冩��(sh霉)閲忥細325,200
銆�銆�DSP Slice 鏁�(sh霉)閲忥細840
銆�銆�Block RAM 绺介噺锛�18MB
銆�銆�鍏�(n猫i)閮ㄩ厤缃�瀛樺劜鍣�锛�26.8Mb
銆�銆�I/O 閵�琛屾暩(sh霉)閲忥細50
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
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銆�銆�鏅傞悩绠＄悊妯″�婏細MMCM 鍜� PLL

XC7K325T-FFG900A 鐨勪富瑕佺壒鎬у寘鎷�锛�
銆�銆�1. 楂樻�ц兘鑸囦綆鍔熻�楋細鍩轰簬 28nm HPL锛圚igh Performance with Low Power锛夊伐钘濇妧琛�(sh霉)锛岃兘澶�?q奴)宕縁(xi脿n)楂樻�ц兘鐨勫悓鏅傞’钁楅檷浣庡姛鑰�銆�
銆�銆�2. 寮峰ぇ鐨勯倧杓�铏曠悊鑳藉姏锛氭搧鏈夎秴閬� 32 钀�鍊嬪彲绶ㄧ▼閭忚集鍠�鍏�锛屾敮鎸佸京(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗗拰绠楁硶瀵︾従(xi脿n)銆�
銆�銆�3. 璞愬瘜鐨� DSP 鏀�鎸侊細鍏�(n猫i)缃� 840 鍊� DSP Slice锛岃兘澶犻珮鏁堝湴閫�(j矛n)琛屼箻娉曠疮鍔犻亱绠楋紝寤ｆ硾鎳�(y墨ng)鐢ㄤ簬瑕栭牷铏曠悊銆佸湒鍍忚瓨鍒ョ瓑闋�(l菒ng)鍩�銆�
銆�銆�4. 澶у�归�� Block RAM锛氱附?c猫)钀樼獰_(d谩)鍒� 18MB锛岃兘澶犳豢瓒冲ぇ瑕�(gu墨)妯℃暩(sh霉)鎿�(j霉)绶╁瓨鐨勯渶姹傦紝鍚屾檪鏀�鎸侀潏娲荤殑鍏�(n猫i)瀛樻槧灏勫姛鑳�銆�
銆�銆�5. 楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛氭敮鎸侀珮閬�(d谩) 6.6 Gb/s 鐨勫偝杓搁�熺巼锛屽吋瀹瑰�氱ó閫氫俊鍗�(xi茅)璀板�� PCIe銆丼ATA 鍜屽崈鍏嗕互澶�缍�(w菐ng)銆�
銆�銆�6. 鍙�鎿�(ku貌)灞曟�у挤锛氭敮鎸佸�氱ó鎺ュ彛妯�(bi膩o)婧�(zh菙n)锛屽寘鎷� LVDS銆丩VCMOS 绛�锛屽苟涓斿叿鍌欓潏娲荤殑鏅傞悩绠＄悊鍜屽京(f霉)浣嶆�熷埗銆�
銆�銆�7. 宓屽叆寮忚檿鐞嗗櫒鏀�鎸侊細鍙�浠ラ�氶亷椤嶅�栫�� IP 鏍稿祵鍏� MicroBlaze 鎴� PowerPC 纭�鏍歌檿鐞嗗��锛屾��(g貌u)寤哄畬鏁寸殑 SoC 绯荤当(t菕ng)銆�
銆�銆�8. 闁嬬櫦(f膩)宸ュ叿瀹屽杽锛歑ilinx 鎻愪緵浜� Vivado Design Suite 绛夐枊鐧�(f膩)宸ュ叿锛屼究浜庣敤鎴跺揩閫熻ō(sh猫)瑷堝拰椹楄瓑 FPGA 鎳�(y墨ng)鐢ㄧ▼搴�銆�

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銆�銆�1. 閫氫俊绯荤当(t菕ng)锛氱敤浜庡熀绔欒ō(sh猫)瑷�銆佷俊铏熻檿鐞嗗拰鍗�(xi茅)璀拌綁(zhu菐n)鎻涚瓑鍔熻兘銆�
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鏀�鎸侀珮娓呰�栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓�炲挤鍜屽�︽檪鍒嗘瀽銆�
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銆�銆�4. 閱�(y墨)鐧傝ō(sh猫)鍌欙細閬╃敤浜庤秴鑱叉尝鎴愬儚銆丆T 鎺冩弿鍎�绛夐珮绔�閱�(y墨)鐧傚櫒姊�銆�
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XC7K325T-2FFG900C
銆�銆�XC7K325T-3FFG900C
銆�銆�XC7K325TFBG676-1
銆�銆�XC7K325TFBG676-2
銆�銆�XC7K325TFBG676-3