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鐢�(ch菐n)鍝佸瀷铏�(h脿o)	XC7K325T-1FBG900C
鎻忚堪	IC FPGA 500 I/O 900FCBGA
鍒嗛(l猫i)	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪)
鐢熺敘(ch菐n)寤犲	Xilinx鍏徃
绯诲垪	Kintex?-7
閮ㄥ垎鐙€鎱�(t脿i)	娲绘€�
闆诲-闆绘簮	0.97V~1.03V
宸ヤ綔婧害	0掳C~85掳C(TJ)
鍖�/绠�	900-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘	900-FCBGA(31x31)
鍩虹(ch菙)閮ㄤ欢铏�(h脿o)	XC7K325T

鐢�(ch菐n)鍝佸湒鐗�

XC7K325T-1FBG900C

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓(l猫i)鍨�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪
绗﹀悎REACH妯�(bi膩o)婧�(zh菙n)	鏄�
绗﹀悎姝愮洘RoHS妯�(bi膩o)婧�(zh菙n)	鏄�
鐙€鎱�(t脿i)	娲绘€�
鏅�(sh铆)閻橀牷鐜�-鏈€澶у€�	1098.0 MHz
CLB-Max鐨勭祫鍚堝欢閬�	0.74 ns
JESD-30浠ｇ⒓	S-PBGA-B900
JESD-609浠ｇ⒓	E1
绺絉AM浣嶆暩(sh霉)	16404480
CLB鏁�(sh霉)閲�	25475.0
杓稿叆鏁�(sh霉)閲�	500.0
閭忚集鍠厓鐨勬暩(sh霉)閲�	326080.0
杓稿嚭鏁�(sh霉)閲�	500.0
绲傜鏁�(sh霉)閲�	900
宸ヤ綔婧害-鏈€灏忓€�	0鈩�
宸ヤ綔婧害-鏈€楂�	85鈩�
绲勭箶	25475 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	鏈(bi膩o)鏄�
闆绘簮	1,1.8,3.3
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
鍧愬Э楂�- 鏈€澶�	2.54姣背
瀛愰(l猫i)鍒�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪
闆绘簮闆诲	1.0 V
闆绘簮闆诲-鏈€灏忓€�	0.97 V
闆绘簮闆诲-鏈€澶у€�	1.03 V
瀹夎椤�(l猫i)鍨�	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆(j铆)	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn96.5Ag3.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绲傜闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴�-鏈€澶у€�(s)	鏈(bi膩o)鏄�
闀�(zh菐ng)搴�	31.0姣背
瀵害	31.0姣背
鍖呰楂旀潗鏂�	濉戞枡/鐠�(hu谩n)姘фü(sh霉)鑴�
鍖呰９浠ｇ⒓	BGA
鍖呯瓑鍍�(ji脿)浠ｇ⒓	BGA900,30X30,40
鍖呰褰㈢媭	寤ｅ牬(ch菐ng)
鍖呰棰�(f膿ng)鏍�	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾�(shu艒)鏄�	FBGA-900

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛(l猫i)

鐒�(w煤)閴涚媭鎱�(t脿i)	鐒�(w煤)閴�
婵曞害鏁忔劅搴︾瓑绱�(j铆)(MSL)	4(72灏忔檪(sh铆))

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楂樻€ц兘SelectIO?鎶€琛�(sh霉)锛屾敮鎸侀珮閬�(d谩)1,866 Mb / s鐨凞DR3鎺ュ彛銆�
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PCIExpress?(PCIe)闆嗘垚妯″锛屾渶澶氬彲鏀寔x8 Gen3绔粸(di菐n)鍜屾牴绔彛瑷�(sh猫)瑷�(j矛)銆�
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鐢ㄦ埗鍙厤缃殑妯℃摤鎺ュ彛(XADC)锛屽寘鍚付鏈夌墖涓婄啽鍜岄浕婧愬偝鎰熷櫒鐨勯洐12浣�1MSPS妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒銆�
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