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XC7K160T-3FBG676C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Kintex-7 绯诲垪 FPGA 鑺墖锛屽爆浜庨珮绔� FPGA 绯诲垪銆傝┎鑺墖鍩轰簬 28nm 鍒剁▼宸ヨ棟瑷▓锛屽叿鏈夐珮鎬ц兘銆佷綆鍔熻�楃殑鐗归粸锛岄仼鍚堢敤浜庡京闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗗拰楂橀�熸帴鍙ｆ噳鐢�銆傚畠闆嗘垚浜嗚睈瀵岀殑 DSP Slice銆丅lock RAM 鍜屽皥鐢ㄧ殑鏀剁櫦(f膩)鍣ㄨ硣婧�锛屽彲婊胯冻閫氫俊銆佽埅绌鸿埅澶�銆佸伐妤�(y猫)鎺у埗浠ュ強閱�(y墨)鐧傛垚鍍忕瓑澶氬�嬮牁(l菒ng)鍩熺殑寰╅洔闇�姹傘��
銆�銆�XC7K160T 鏄┎绯诲垪涓殑涓�娆句腑绔瀷铏�锛屽叿鏈夐仼涓殑閭忚集鍠厓鏁�(sh霉)閲忓拰瀛樺劜璩囨簮锛岃兘澶犻潏娲绘噳灏嶅绋ō瑷堥渶姹傘�傚叾灏佽褰㈠紡鐐� FBG676锛團ine-Pitch Ball Grid Array锛�锛屽伐浣滈�熷害绛夌礆鐐� -3锛屼唬琛ㄤ簡鐩稿皪杓冮珮鐨勬�ц兘琛ㄧ従(xi脿n)銆�
鍨嬭櫉锛歑C7K160T-3FBG676C
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛欿intex-7
銆�銆�鍒剁▼宸ヨ棟锛�28nm
銆�銆�閭忚集鍠厓鏁�(sh霉)锛�162,500
銆�銆�DSP Slice 鏁�(sh霉)閲忥細1,080
銆�銆�Block RAM锛氱磩 14Mb
銆�銆�I/O 鏁�(sh霉)閲忥細536
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂橀仈 12.5 Gbps
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹� 0.9V锛孖/O 闆诲鏍规摎(j霉)閰嶇疆涓嶅悓鍙湪 1.8V 鑷� 3.3V 鑼冨湇鍏�(n猫i)瑾�(di脿o)鏁�
銆�銆�灏佽褰㈠紡锛欶BG676
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 85掳C锛�
XC7K160T-3FBG676C 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鑸囬潏娲绘��銆傚畠鐨勪富瑕佺壒榛炲寘鎷細
銆�銆�1. 楂樻�ц兘鏋舵(g貌u)锛氶噰鐢� UltraScale 鏋舵(g貌u)鐨勬棭鏈熺増鏈紝鏀寔寰╅洔鐨勯倧杓亱绠楀拰骞惰铏曠悊鑳藉姏銆�
銆�銆�2. 璞愬瘜鐨� DSP 璩囨簮锛氬収(n猫i)缃閬� 1,080 鍊� DSP Slice锛岄仼鐢ㄤ簬楂樼簿搴︽诞榛為亱绠楀拰婵炬尝绠楁硶銆�
銆�銆�3. 澶у閲忓瓨鍎茶硣婧愶細鎻愪緵绱� 14Mb 鐨� Block RAM锛屾敮鎸佸京闆滅殑宓屽叆寮忓瓨鍎插姛鑳�銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鏀寔楂橀仈 12.5 Gbps 鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛屾豢瓒崇従(xi脿n)浠ｉ�氫俊绯荤当(t菕ng)鐨勫付瀵渶姹�銆�
銆�銆�5. 闈堟椿鐨� I/O 鎺ュ彛锛氭敮鎸佸绋婧栧崝(xi茅)璀�锛屼緥濡� PCIe銆丏DR3銆佸崈鍏嗕互澶恫(w菐ng)绛�銆�
銆�銆�6. 鍏�(n猫i)缃檪閻樼鐞嗗柈鍏冿細闆嗘垚 PLL 鍜� MMCM 妯″锛屾柟渚跨敓鎴愮簿纰虹殑鏅傞悩淇¤櫉銆�
銆�銆�7. 鍔熻�楀劒(y艒u)鍖栨妧琛�(sh霉)锛氶�氶亷鍕曟厠(t脿i)鍔熻�楃鐞嗗拰闆绘簮鍩熼殧闆㈡妧琛�(sh霉)闄嶄綆鏁撮珨鍔熻��銆�
銆�銆�8. 鏄撲簬闁嬬櫦(f膩)锛氶厤鍚� Vivado Design Suite 宸ュ叿閺�锛屽彲浠ュ揩閫熷鐝�(xi脿n)瑷▓椹楄瓑鍜岄儴缃�銆�
XC7K160T-3FBG676C 寤ｆ硾鎳夌敤浜庡鍊嬮牁(l菒ng)鍩燂紝鍖呮嫭浣嗕笉闄愪簬锛�
銆�銆�1. 閫氫俊瑷倷锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙绛�锛屽埄鐢ㄥ叾楂橀�熶覆琛屾敹鐧�(f膩)鍣ㄥ鐝�(xi脿n)鏁�(sh霉)鎿�(j霉)鍌宠几銆�
銆�銆�2. 瑕栭牷铏曠悊锛氶仼鐢ㄤ簬瑕栭牷绶ㄧ⒓銆佽В纰煎強鍦栧儚澧炲挤绛夐牁(l菒ng)鍩燂紝寰楃泭浜庡叾寮峰ぇ鐨勫苟琛岃▓绠楄兘鍔涖��
銆�銆�3. 閱�(y墨)鐧傞浕瀛愶細濡傝秴鑱叉尝鎴愬儚绯荤当(t菕ng)锛屽埄鐢� FPGA 瀵︾従(xi脿n)瀵︽檪淇¤櫉铏曠悊銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ綔閬嬪嫊鎺у埗鍣ㄦ垨鍒嗗竷寮忔帶鍒剁郴绲�(t菕ng)鐨勬牳蹇冭檿鐞嗗櫒銆�
銆�銆�5. 鑸┖鑸ぉ锛氬洜鍏跺彲闈犳�э紝鍦ㄨ(w猫i)鏄熼�氫俊鍜岄琛屾帶鍒朵腑鏈夊唬娉涙噳鐢�銆�
銆�銆�6. 娓│娓噺锛氬绀烘尝鍣ㄥ拰淇¤櫉鐧�(f膩)鐢熷櫒绛夎ō鍌欎腑锛屼綔鐐烘牳蹇冭檿鐞嗗柈鍏�銆�
XC7K160T-2FBG676C
銆�銆�XC7K160T-1FBG676C
銆�銆�XC7K160T-3FFG676C
