鍨嬭櫉(h脿o)锛歑C7A50T-L2CSG324E
銆�銆�閭忚集鍠�鍏冩��(sh霉)锛�50600
銆�銆�RAM锛氱磩 2.9 Mb (鍒嗗竷鍦� Block RAM 鍜� Distributed RAM 涓�)
銆�銆�DSP Slice 鏁�(sh霉)閲忥細120
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細206
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster SPI銆丼lave SPI銆丅PI
銆�銆�灏佽�濓細CSG324
銆�銆�宸ヨ棟锛�28nm HPL (High-Performance, Low-Power)
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏細鍟嗘��(y猫)绱�(j铆)锛�0掳C 鑷� +85掳C锛�
銆�銆�闆绘簮闆诲�擄細Vccint = 1.0V 卤 0.05V; Vccaux = 1.8V 卤 0.15V

XC7A50T-L2CSG324E 鎻愪緵浜嗗挤(qi谩ng)澶х殑纭�浠跺姛鑳藉拰闈堟椿鎬э細
銆�銆�1. 楂樻�ц兘鏋舵��(g貌u)锛氭敮鎸侀珮閬�(d谩) 633 MHz 鐨勭敤鎴舵檪(sh铆)閻橀牷鐜�銆�
銆�銆�2. 鍏�(n猫i)缃�纭�鏍告ā濉婏細濡� PCIe Gen2 x1 妯″��锛屽彲鐢ㄤ簬蹇�閫熷��(sh铆)鐝�(xi脿n)鏁�(sh霉)鎿�(j霉)鍌宠几銆�
銆�銆�3. 澶氱ó瀛樺劜(ch菙)閬搁爡(xi脿ng)锛氬寘鎷� Block RAM銆丏istributed RAM 鍜� FIFO 绲�(ji茅)妲�(g貌u)锛屾豢瓒充笉鍚屽瓨鍎�(ch菙)闇�姹�銆�
銆�銆�4. DSP Slice 鏀�鎸侊細姣忓��(g猫) DSP Slice 鍖呭惈 27x18 浣嶄箻娉曞櫒鍜屽姞娉曞櫒锛岄仼鍚堟暩(sh霉)瀛椾俊铏�(h脿o)铏曠悊浠诲嫏(w霉)銆�
銆�銆�5. 浣庡姛鑰楄ō(sh猫)瑷�(j矛)锛氶�氶亷 PowerScale 鎶�琛�(sh霉)鍎�(y艒u)鍖栧嫊(d貌ng)鎱�(t脿i)鍔熻�楋紝鍦ㄩ檷浣庡姛鑰楃殑鍚屾檪(sh铆)淇濇寔楂樻�ц兘銆�
銆�銆�6. 宓屽叆寮忚檿鐞嗗櫒鏀�鎸侊細鍙�浠ラ泦鎴� MicroBlaze 鎴� ARM Cortex-M3 铏曠悊鍣ㄩ��(j矛n)琛岃粺鏍告垨纭�鏍歌檿鐞嗐��
銆�銆�7. 楂橀�熸敹鐧�(f膩)鍣�锛氭敮鎸侀�熺巼楂橀仈(d谩) 6.6 Gbps 鐨勪覆琛屾帴鍙�锛岄仼鐢ㄤ簬楂橀�熸暩(sh霉)鎿�(j霉)鍌宠几鍫�(ch菐ng)鏅�銆�
銆�銆�8. 鍙�闈犳�ч珮锛氭彁渚涘柈浜嬩欢缈昏綁(zhu菐n)闃茶��(h霉)锛圫EU Mitigation锛夛紝澧炲挤(qi谩ng)鍙�闈犳�т互閬╂噳(y墨ng)鎯″姡鐠�(hu谩n)澧冧笅鐨勬噳(y墨ng)鐢�銆�
銆�銆�9. 鏄撶敤闁嬬櫦(f膩)宸ュ叿锛歑ilinx 鎻愪緵鐨� Vivado Design Suite 鍜� ISE Design Suite 鑳藉�犲公鍔╁伐绋嬪斧楂樻晥瀹屾垚瑷�(sh猫)瑷�(j矛)銆佷豢鐪熷強瑾�(di脿o)瑭﹂亷绋嬨��

瑭茶姱鐗囧唬娉涙噳(y墨ng)鐢ㄤ簬澶氬��(g猫)闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊瑷�(sh猫)鍌欙細濡傜劇绶氬熀绔�銆佺恫(w菐ng)绲�(lu貌)浜ゆ彌姗�(j墨)鍜岃矾鐢卞櫒涓�鐨勪俊铏�(h脿o)铏曠悊閮ㄥ垎銆�
銆�銆�2. 閱�(y墨)鐧傛垚鍍忥細瓒呰伈娉�銆丆T 鎺冩弿鍎�绛夐渶瑕佸��(sh铆)鏅�(sh铆)鍦栧儚铏曠悊鐨勮ō(sh猫)鍌�銆�
銆�銆�3. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栵細閬�(y霉n)鍕�(d貌ng)鎺у埗鍣ㄣ�佹��(j墨)鍣ㄤ汉瑕栬�虹郴绲�(t菕ng)銆�
銆�銆�4. 娑堣不(f猫i)椤為浕瀛愮敘(ch菐n)鍝侊細楂樻竻瑕栭牷绶ㄨВ纰笺�佸湒褰㈠姞閫熺瓑鍔熻兘妯″��銆�
銆�銆�5. 娓�(c猫)瑭︽脯(c猫)閲�?j墨)x鍣�锛氱ず娉㈠��銆佷俊铏�(h脿o)鐧�(f膩)鐢熷櫒绛夐渶瑕佸揩閫熸暩(sh霉)鎿�(j霉)閲囬泦鑸囧垎鏋愮殑鍫�(ch菐ng)鍚�銆�
銆�銆�6. 宓屽叆寮忚▓(j矛)绠楀钩鑷�(t谩i)锛氶亱(y霉n)琛屾搷浣滅郴绲�(t菕ng)骞跺煼(zh铆)琛屽京(f霉)闆滅畻娉曠殑楂樻�ц兘宓屽叆寮忕郴绲�(t菕ng)銆�

XC7A50T-2FGG484I, XC7A50T-2FTG256E, XC7A50T-2CSG324C