鏅傞枔锛�2025/4/25 17:55:29
闁辫畝锛�44
XC7A50T-L1CPG236I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA 鑺墖锛岃┎绯诲垪鑺墖涓昏闈㈠悜浣庡姛鑰�銆侀珮鎬ц兘鐨勬噳鐢ㄩ渶姹�銆侫rtix-7 绯诲垪鍩轰簬 28nm 宸ヨ棟鍒剁▼瑷▓锛屾彁渚涜睈瀵岀殑閭忚集璩囨簮銆佹暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″浠ュ強楂橀�熶覆琛屾敹鐧�(f膩)鍣ㄧ瓑鍔熻兘銆傛鍨嬭櫉閬╃敤浜庡悇绋祵鍏ュ紡绯荤当(t菕ng)銆侀�氫俊瑷倷銆侀啱(y墨)鐧傚奖鍍忓拰宸ユキ(y猫)鎺у埗绛夐牁鍩熴��
銆�銆�XC7A50T 琛ㄧず鍏跺収(n猫i)閮ㄥ寘鍚ぇ绱� 50K 鐨勯倧杓柈鍏冿紙Logic Cells锛�锛孡1 妯欒瓨鍏堕�熷害绛夌礆鐐� -1锛孋PG236 琛ㄧず灏佽椤炲瀷鐐� CPG236锛�236 寮曡叧鐨勭悆鏌甸櫍鍒楀皝瑁濓級锛孖 琛ㄧず宸ヤ綔婧害鑼冨湇鐐哄伐妤�(y猫)绱氾紙-40掳C 鑷� +85掳C锛�銆�
鍨嬭櫉锛歑C7A50T-L1CPG236I
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細50K
銆�銆�宸ヨ棟鍒剁▼锛�28nm
銆�銆�灏佽椤炲瀷锛欳PG236
銆�銆�宸ヤ綔闆诲锛�0.9V 鑷� 1.0V
銆�銆�閰嶇疆妯″紡锛歋electMAP 鍜� JTAG
銆�銆�瀛樺劜鍣ㄨ硣婧愶細绱� 2.9Mb Block RAM
銆�銆�DSP Slice 鏁�(sh霉)閲忥細100 鍊�
銆�銆�鐢ㄦ埗 I/O 鏁�(sh霉)閲忥細169 鍊�
銆�銆�鏀寔鐨勬渶澶ф檪閻橀牷鐜囷細瓒呴亷 500MHz
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�渚涢浕鎺ュ彛锛氬闆绘簮鍩熸灦妲�
銆�銆�鏁�(sh霉)鎿�(j霉)鎵嬪唺鐗堟湰锛歷3.1
XC7A50T-L1CPG236I 鍏锋湁浠ヤ笅椤憲鐗规�э細
銆�銆�1. 楂樻�ц兘鑸囦綆鍔熻�楋細閲囩敤 28nm 宸ヨ棟鍒堕�狅紝绲愬悎 UltraScale 鏋舵鎶�琛�锛屽彲瀵︾従(xi脿n)鏇撮珮鐨勬�ц兘鍚屾檪淇濇寔杓冧綆鐨勫姛鑰椼��
銆�銆�2. 闈堟椿鐨勯倧杓硣婧愶細50K 閭忚集鍠厓瓒充互婊胯冻涓皬鍨嬭ō瑷堥渶姹�锛屽悓鏅傞倓鎻愪緵浜嗚睈瀵岀殑甯冪窔璩囨簮浠ュ劒(y艒u)鍖栦俊铏熷畬鏁存�с��
銆�銆�3. 宓屽叆寮� DSP 鏀寔锛氬収(n猫i)缃閬� 100 鍊� DSP Slice锛岃兘澶犻珮鏁堝畬鎴愬京闆滄暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕欍��
銆�銆�4. 澶у閲忓瓨鍎插櫒锛氶厤鍌欑磩 2.9Mb 鐨勫垎甯冨紡 Block RAM锛屽彲鐢ㄤ簬绶╁瓨鎴�?q奴)宕縁(xi脿n) FIFO 绛夊姛鑳�銆�
銆�銆�5. 楂橀�熶覆琛屾帴鍙ｏ細鏀寔楂橀仈 6.6Gbps 鐨� GTX 鏀剁櫦(f膩)鍣�锛岄仼鍚堝绋珮閫熼�氫俊鍗�(xi茅)璀般��
銆�銆�6. 鍙摯灞曟�у挤锛氭敮鎸佸绋瑷�ｆ帴锛屽寘鎷� PCIe銆乁SB銆佸崈鍏嗕互澶恫(w菐ng)绛�銆�
銆�銆�7. 鏄撲簬绶ㄧ▼鍜岃(di脿o)瑭︼細閫氶亷 Vivado Design Suite 鎻愪緵寮峰ぇ鐨勯枊鐧�(f膩)宸ュ叿鏀寔锛岀啊鍖栬ō瑷堟祦绋�銆�
瑭插瀷铏� FPGA 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬瀵︽檪鏁�(sh霉)鎿�(j霉)閲囬泦銆侀亱鍕曟帶鍒跺拰姗熷櫒浜鸿瑕�銆�
銆�銆�2. 閱�(y墨)鐧傝ō鍌欙細濡傝秴鑱叉尝鎴愬儚銆丆T 鎺冩弿鍎�涓殑淇¤櫉铏曠悊鍠厓銆�
銆�銆�3. 閫氫俊鍩虹瑷柦锛氬皬鍨嬪熀绔�銆佽矾鐢卞櫒鍙婄恫(w菐ng)绲′氦鎻涙鐨勬牳蹇冭檿鐞嗗櫒銆�
銆�銆�4. 瑕栭牷鐩�(ji膩n)鎺э細瑕栭牷绶ㄨВ纰煎姞閫熷櫒鎴栧湒鍍忛爯铏曠悊妯″銆�
銆�銆�5. 姹借粖闆诲瓙锛欰DAS锛堥珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛変腑鐨勫偝鎰熷櫒铻嶅悎鍜屾暩(sh霉)鎿�(j霉)铏曠悊銆�
銆�銆�6. 鑸┖鑸ぉ锛氭姉杓诲皠鍔犲浐鍚庣殑鐗堟湰閬╃敤浜庣┖闁撶挵(hu谩n)澧冧笅鐨勯棞閸典换鍕欒▓绠�銆�
銆�銆�7. 鏁欒偛绉戠爺锛氫綔鐐烘暀瀛稿钩鑷烘垨?q奴)宥掔倶O鍌欎腑鐨勬牳蹇冨櫒浠躲��
XC7A50T-1CPG236C, XC7A50T-2CPG236I, XC7A50T-3CPG236C
