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鍨嬭櫉锛歑C7A15T-2CSG324C
銆€銆€绯诲垪锛欰rtix-7
銆€銆€鍒堕€犲伐钘濓細28nm
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細绱� 15,000
銆€銆€閰嶇疆瀛樺劜鍣ㄩ鍨嬶細Block RAM 鍜� Distributed RAM
銆€銆€DSP Slice 鏁�(sh霉)閲忥細90
銆€銆€鍏�(n猫i)閮ㄥ瓨鍎插櫒瀹归噺锛氱磩 640 KB
銆€銆€I/O 閵€琛屾暩(sh霉)閲忥細24
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆€銆€渚涢浕闆诲锛氭牳蹇冮浕澹� 1.0V锛孖/O 闆诲 1.8V/2.5V/3.3V
銆€銆€灏佽褰㈠紡锛欳SG324

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1. XC7A15T-2CSG324C 鎻愪緵浜嗗挤澶х殑鍙法绋嬮倧杓硣婧�锛屽寘鎷� LUT锛堟煡鎵捐〃锛�銆佽Ц鐧�(f膩)鍣ㄥ拰閫蹭綅閺堢瓑锛屾敮鎸佸京(f霉)闆滅畻娉曞拰鏁�(sh霉)鎿�(j霉)璺緫鐨勮ō(sh猫)瑷�銆�
銆€銆€2. 鍏�(n猫i)缃� DSP Slice 鏀寔楂樻晥鐨勪箻娉曠疮鍔犻亱绠楋紝閬╁悎鏁�(sh霉)瀛椾俊铏熻檿鐞嗘噳(y墨ng)鐢�銆�
銆€銆€3. 鏀寔楂橀仈 6.6 Gbps 鐨� GTX 鏀剁櫦(f膩)鍣�锛屽彲鐢ㄤ簬楂橀€熶覆琛屾帴鍙ｈō(sh猫)瑷�銆�
銆€銆€4. 鍏�(n猫i)閮� Block RAM 鍜� Distributed RAM 鎻愪緵浜嗚睈瀵岀殑瀛樺劜鍣ㄨ硣婧�锛岃兘澶�?q奴)宕縁(xi脿n) FIFO銆佺珐瀛樺拰灏忓瀷 ROM 绛夊姛鑳�銆�
銆€銆€5. 鎻愪緵澶氱ó I/O 妯欐簴鏀寔锛屽 LVCMOS銆丩VDS 鍜屽樊鍒嗕俊铏熷偝杓�锛屾豢瓒冲妯ｅ寲鎺ュ彛闇€姹�銆�
銆€銆€6. 鏀寔閮ㄥ垎閲嶆柊閰嶇疆鍔熻兘锛屽厑瑷卞湪閬嬭鏅傚嫊鎱�(t脿i)鏇存柊 FPGA 鐨勬煇浜涘崁(q奴)鍩�锛屽緸鑰屾彁楂樼郴绲�(t菕ng)闈堟椿鎬�銆�
銆€銆€7. 闆嗘垚浜嗛帠鐩哥挵(hu谩n) (PLL) 鍜屾檪閻樼鐞嗘ā濉婏紝鎻愪緵绮剧⒑鐨勬檪閻樺垎閰嶅拰绠＄悊鍔熻兘銆�
銆€銆€8. 閲囩敤浣庡姛鑰� 28nm 宸ヨ棟鎶€琛�(sh霉)锛岄仼鍚堝皪鍔熻€楁晱鎰熺殑鎳�(y墨ng)鐢ㄥ牬鏅�銆�

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