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鐗归粸

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涓枃鍙冩暩(sh霉)

鍟嗗搧鍒嗛	FPGA鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪	闆诲-渚涢浕	0.95V ~ 1.05V
鍝佺墝	XILINX(璩介潏鎬�)	瀹夎椤炲瀷	琛ㄩ潰璨艰鍨�
灏佽	484-FBGA锛�23x23锛�	宸ヤ綔婧害	0掳C ~ 85掳C锛圱J锛�
鍟嗗搧妯�(bi膩o)绨�	宸ユキ(y猫)绱�	鍩烘湰鐢�(ch菐n)鍝佺法铏�	XC7A100
閭忚集鍏冧欢/鍠厓鏁�(sh霉)	101440	LAB/CLB鏁�(sh霉)	7925
绺�RAM浣嶆暩(sh霉)	4976640	婵曟埃鏁忔劅鎬х瓑绱�(MSL)	3锛�168 灏忔檪锛�
I/O鏁�(sh霉)	285