鍣ㄤ欢椤炲瀷锛欶PGA
銆�銆�绯诲垪锛欰rtix-7
銆�銆�鍨嬭櫉(h脿o)锛歑C7A100T-1FTG256I
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細104,960
銆�銆�RAM 璩囨簮锛氱磩 2.2 MB锛堝寘鎷� Block RAM 鍜� Distributed RAM锛�
銆�銆�DSP Slice 鏁�(sh霉)閲忥細240
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Artix-7 绯诲垪 FPGA 鎻愪緵浜嗗嚭鑹茬殑鎬ц兘鑸囦綆鍔熻�楄〃鐝�(xi脿n)銆�
銆�銆�1. XC7A100T 閰嶅倷浜嗗ぇ閲忛倧杓�鍠�鍏冿紙Logic Cells锛�锛屽彲瀵�(sh铆)鐝�(xi脿n)寰�(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏�(h脿o)铏曠悊鍔熻兘銆�
銆�銆�2. 鍏�(n猫i)缃�楂樻�ц兘 DSP48E1 妯″��锛屾敮鎸佹诞榛�(di菐n)閬�(y霉n)绠楀拰瀹氶粸(di菐n)閬�(y霉n)绠�锛岀壒鍒ラ仼鍚堟暩(sh霉)瀛�(xu茅)瀵嗛泦鍨嬭▓(j矛)绠椾换鍕�(w霉)銆�
銆�銆�3. 鎻愪緵澶氱ó椤炲瀷鐨勫瓨鍎�(ch菙)鍣ㄨ硣婧�锛屽�� Block RAM 鍜� Distributed RAM锛屾豢瓒充笉鍚屾暩(sh霉)鎿�(j霉)瀛樺劜(ch菙)闇�姹傘��
銆�銆�4. 鏀�鎸� PCIe Gen1/Gen2 鍗�(xi茅)璀�锛屼究浜庣郴绲�(t菕ng)鎿�(ku貌)灞曞拰浜掕伅(li谩n)銆�
銆�銆�5. 闆嗘垚浜嗛珮閫熸敹鐧�(f膩)鍣�锛岄�熺巼鍙�閬�(d谩) 1.25 Gbps 鑷� 6.6 Gbps锛岄仼閰嶅�氱ó鎺ュ彛鍗�(xi茅)璀般��
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銆�銆�7. 鏀�鎸佸�氱ó閰嶇疆妯″紡锛屽寘鎷�鍠�鑺�鐗� SPI Flash 鑷�鍟熷��(d貌ng)鍔熻兘銆�
銆�銆�8. 鍦ㄥ姛鑰楀劒(y艒u)鍖栨柟闈�锛孹ilinx 鎻愪緵浜� Vivado Design Suite 宸ュ叿锛屽公鍔╃敤鎴堕�氶亷鏅�(sh铆)閻橀杸鎺�銆佸嫊(d貌ng)鎱�(t脿i)闆绘簮绠＄悊绛夋墜娈甸檷浣庢暣楂斿姛鑰�銆�

XC7A100T-1FTG256I 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊瑷�(sh猫)鍌欙細灏忓瀷鍩虹珯銆佺恫(w菐ng)闂�(gu膩n)銆佽矾鐢卞櫒绛�銆�
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銆�銆�4. 寤ｆ挱瑕栭牷锛氬湒鍍忚檿鐞�銆佹牸寮忚綁(zhu菐n)鎻�銆佽�栭牷绶ㄧ⒓瑙ｇ��銆�
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銆�銆�6. 宓屽叆寮忚�栬�猴細鏀濆儚闋� ISP 铏曠悊銆佸湒鍍忚瓨(sh铆)鍒ラ爯(y霉)铏曠悊銆�
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XC7A100T-2FTG256I
銆�銆�XC7A100T-3FTG256C
銆�銆�XC7A100T-2CSG324C
銆�銆�XC7A100T-3CSG324I