鍨嬭櫉(h脿o)锛歑C6VSX475T-1FFG1156I
銆�銆�灏佽�濓細FFG1156
銆�銆�閫熷害绛夌礆(j铆)锛�-1
銆�銆�FPGA 绯诲垪锛歏irtex-6
銆�銆�瀛愮郴鍒楋細SX
銆�銆�閭忚集鍠�鍏冩��(sh霉)锛氱磩 47.5 钀�鍊�(g猫)
銆�銆�Block RAM锛�28.9Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2340 鍊�(g猫)
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 840 鍊�(g猫)
銆�銆�Transceiver 鏁�(sh霉)閲忥細24 鍊�(g猫) GTH 鏀剁櫦(f膩)鍣�
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�鍒剁▼宸ヨ棟锛�40nm

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XC6VSX475T-2FFG1156I
銆�銆�XC6VSX475T-3FFG1156I