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XC6VLX550T-1FFG1759C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-6 绯诲垪 FPGA 鑺墖涓殑涓�鍝°�傝┎绯诲垪鑺墖鍩轰簬 40nm 鍒剁▼宸ヨ棟锛屾彁渚涗簡楂樻�ц兘銆侀珮閭忚集瀵嗗害浠ュ強璞愬瘜鐨� DSP 鍜屼覆琛屾敹鐧�(f膩)鍣ㄨ硣婧�銆俋C6VLX550T 鍏锋湁瓒呴亷 55 钀�嬮倧杓柈鍏�锛岄仼鍚堢敤浜庨珮绔▓绠�銆侀�氫俊鍩虹瑷柦銆佸湒鍍忚檿鐞嗗拰杌嶄簨鎳夌敤绛夊京闆滅郴绲�(t菕ng)瑷▓銆�
銆�銆�姝ゅ瀷铏熶腑鐨勫叿楂斿弮鏁�(sh霉)濡備笅锛�'XC6VLX550T' 琛ㄧず Virtex-6 绯诲垪 LX 瀹舵棌鐨� XC6VLX550 鍣ㄤ欢锛�'-1' 琛ㄧず閫熷害绛夌礆鐐� -1锛�'FFG1759' 琛ㄧず灏佽褰㈠紡鐐� FFG1759锛�1759 寮曡叧锛�锛�'C' 琛ㄧず鍟嗘キ(y猫)绱氭韩搴﹁寖鍦嶏紙0掳C 鑷� +85掳C锛�銆�
閭忚集鍠厓鏁�(sh霉)锛�553,760
銆�銆�RAM 绺介噺锛�42.8Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2,160
銆�銆�I/O 鏁�(sh霉)閲忥細940
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster SPI銆丼lave SPI銆丅oundary Scan
銆�銆�宸ヤ綔闆诲锛�1.0V 鏍稿績闆诲 / 1.8V 鎴� 3.3V I/O 闆诲
銆�銆�灏佽锛欶FG1759 (1759 寮曡叧)
銆�銆�婧害鑼冨湇锛�0掳C 鑷� +85掳C (鍟嗘キ(y猫)绱�)
銆�銆�鍒剁▼宸ヨ棟锛�40nm
銆�銆�涓茶鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲忥細36
銆�銆�涓茶鏀剁櫦(f膩)鍣ㄩ�熺巼锛�3.125Gbps 鑷� 6.5Gbps
XC6VLX550T 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鍜岄潏娲绘�э紝鏀寔澶氱ó楂樼礆鍔熻兘锛�
銆�銆�1. 楂樺付瀵覆琛岄�ｆ帴锛氶泦鎴愬閬� 36 鍊� GTP 鏀剁櫦(f膩)鍣�锛屾敮鎸佸緸 PCIe Gen2 鍒� CPRI 绛夊绋珮閫熷崝(xi茅)璀�銆�
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銆�銆�5. 浣庡姛鑰楁灦妲嬶細閫氶亷 PowerPro 鎶�琛撳劒(y艒u)鍖栭潨鎱�(t脿i)鍜屽嫊鎱�(t脿i)鍔熻��锛岄檷浣庢暣楂旂郴绲�(t菕ng)鑳借��銆�
XC6VLX550T 寤ｆ硾鎳夌敤浜庨渶瑕侀珮鎬ц兘鍜岄珮閭忚集瀵嗗害鐨勯牁鍩燂細
銆�銆�1. 閫氫俊瑷倷锛氬寘鎷熀绔�銆佽矾鐢卞櫒鍜屼氦鎻涙鐨勬牳蹇冭檿鐞嗘ā濉娿��
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XC6VLX550T-2FFG1759C
銆�銆�XC6VLX550T-1FFG1156C
銆�銆�XC6VLX550T-2FFG1156C
