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XC6VLX365T-2FFG1759C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-6 绯诲垪 FPGA 鑺墖銆傝┎绯诲垪鑺墖鍩轰簬鍏堥�茬殑 40nm 宸ヨ棟鎶�琛�(sh霉)锛屽叿鏈夐珮鎬ц兘銆佷綆鍔熻�楀拰楂樺害闈堟椿鎬х殑鐗归粸锛岄仼鐢ㄤ簬澶氱ó寰╅洔鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕欏拰宓屽叆寮忕郴绲�(t菕ng)闁嬬櫦(f膩)銆俋C6VLX365T-2FFG1759C 鎻愪緵浜嗚睈瀵岀殑閭忚集璩囨簮銆佸瓨鍎插櫒濉�銆丏SP Slice 鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣紝鏀寔寤ｆ硾鐨勬噳鐢ㄥ牬鏅�锛屼緥濡傞�氫俊鍩虹瑷柦銆佽闋昏垏鍦栧儚铏曠悊銆佹脯瑭︽脯閲忚ō鍌欎互鍙婂伐妤�(y猫)鑷嫊鍖栫瓑銆�
鍨嬭櫉锛歑C6VLX365T-2FFG1759C
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歏irtex-6
銆�銆�宸ヨ棟鍒剁▼锛�40nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 363,600 鍊�
銆�銆�DSP Slice 鏁�(sh霉)閲忥細840 鍊�
銆�銆�Block RAM 瀹归噺锛�11.4 Mb
銆�銆�閰嶇疆妯″紡锛歋electMAP 鎴� Master SPI
銆�銆�I/O 寮曡叧鏁�(sh霉)锛氭渶澶� 848 鍊�
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�灏佽褰㈠紡锛欶FG1759
銆�銆�閫熷害绛夌礆锛�-2
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XC6VLX365T-3FFG1759C
銆�銆�XC6VLX365T-1FFG1759C
