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XC6VLX240T-L2FFG1759I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-6 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏�銆傝┎绯诲垪 FPGA 閲囩敤 40nm 鍒堕�犲伐钘濓紝鎻愪緵楂樻�ц兘銆佷綆鍔熻�楀拰楂樺害闈堟椿鎬х殑瑙ｆ焙鏂规銆俋C6VLX240T 灞簬 LX 绯诲垪锛屽叿鏈夎睈瀵岀殑閭忚集璩囨簮鍜� DSP 妯″锛岄仼鐢ㄤ簬楂樼淇¤櫉铏曠悊銆侀�氫俊绯荤当(t菕ng)銆佸湒鍍忚檿鐞嗕互鍙婂伐妤�(y猫)鎺у埗绛夐牁鍩�銆�
銆�銆�姝よ姱鐗囧叿鍌欏ぇ瀹归噺鐨勯倧杓柈鍏�銆侀珮閫熶覆琛屾敹鐧�(f膩)鍣�銆佸祵鍏ュ紡瀛樺劜鍣ㄤ互鍙婇潏娲荤殑鏅傞悩绠＄悊鍔熻兘锛屽彲婊胯冻寰╅洔瑷▓鐨勯渶姹�銆�
鍣ㄤ欢椤炲瀷锛欶PGA
銆�銆�绯诲垪锛歏irtex-6 LX
銆�銆�灏佽锛欶FG1759
銆�銆�閫熷害绛夌礆锛�-L2
銆�銆�閰嶇疆妯″紡锛歋electMAP, JTAG
銆�銆�閭忚集鍠厓鏁�(sh霉)锛氱磩 240K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細1380
銆�銆�Block RAM锛氱磩 12.9Mb
銆�銆�鍏�(n猫i)閮� Flash锛氱劇
銆�銆�鐢ㄦ埗 I/O 寮曡叧鏁�(sh霉)锛�1096
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�闆绘簮闆诲锛氭牳蹇冮浕澹� 1.0V锛岃紨鍔╅浕澹� 2.5V/3.3V
1. 楂樻�ц兘鏋舵鏀寔楂橀仈 550 MHz 鐨勬檪閻橀牷鐜�銆�
銆�銆�2. 鍏�(n猫i)缃珮閫熶覆琛屾敹鐧�(f膩)鍣紙GTX锛夛紝鍌宠几閫熺巼鍙仈 6.5 Gbps銆�
銆�銆�3. 鎻愪緵澶ч噺 DSP Slice锛岀敤浜庡劒(y艒u)鍖栨暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�銆�
銆�銆�4. 鍖呭惈澶氱ó宓屽叆寮忓瓨鍎插櫒妯″锛屽 Block RAM 鍜� Distributed RAM銆�
銆�銆�5. 鏀寔 DDR2/DDR3 鍏�(n猫i)瀛樻帴鍙�锛屾暩(sh霉)鎿�(j霉)鍌宠几甯跺楂樸��
銆�銆�6. 闆嗘垚 PCIe 纭牳妯″锛屼究浜庡鐝�(xi脿n)楂橀�熶簰鑱�(li谩n)銆�
銆�銆�7. 鏀寔澶氱ó閰嶇疆鏂瑰紡锛屽寘鎷緸 SPI Flash 鍟熷嫊鎴栭�氶亷澶栭儴涓绘绶ㄧ▼鍔犺級銆�
銆�銆�8. 鎻愪緵闈堟椿鐨勬檪閻樼鐞嗙郴绲�(t菕ng)锛屽寘鍚� PLL 鍜� DCM 妯″銆�
銆�銆�9. 鏀寔閮ㄥ垎閲嶆柊閰嶇疆鎶�琛�锛屽厑瑷卞湪閬嬭鏅傚嫊鎱�(t脿i)鏇存柊鍔熻兘妯″銆�
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銆�銆�2. 瑕栭牷鍜屽湒鍍忚檿鐞嗙郴绲�(t菕ng)锛屽閱�(y墨)鐧傛垚鍍�銆佺洠(ji膩n)鎺ф敐鍍忔鍜屽濯掗珨绶ㄧ⒓瑙ｇ⒓銆�
銆�銆�3. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�熷崱鍜岄珮鎬ц兘瑷堢畻骞宠嚭銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栧拰瀵︽檪鎺у埗绯荤当(t菕ng)銆�
銆�銆�5. 娓│鑸囨脯閲忓剙鍣紝濡傜ず娉㈠櫒鍜屼俊铏熺櫦(f膩)鐢熷櫒銆�
銆�銆�6. 杌嶄簨鍜岃埅澶╅牁鍩熶腑鐨勪俊铏熻檿鐞嗗拰闆烽仈绯荤当(t菕ng)銆�
銆�銆�7. 宓屽叆寮忚瑕虹郴绲�(t菕ng)鍜岃嚜鍕曢椐涜紨鍔╃郴绲�(t菕ng)涓殑寰╅洔绠楁硶瀵︾従(xi脿n)銆�
XC6VLX240T-2FFG1759I
銆�銆�XC6VLX240T-3FFG1759I
