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闁辫畝锛�21
XC6SLX9-3FTG256I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Spartan-6 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏熴�係partan-6 绯诲垪灞簬浣庢垚鏈� FPGA锛屽唬娉涙噳鐢ㄤ簬宸ユキ(y猫)鎺у埗銆侀�氫俊瑷倷銆佹秷璨婚浕瀛愪互鍙婂祵鍏ュ紡铏曠悊绛夐牁鍩�銆�
銆�銆�瑭茶姱鐗囬噰鐢ㄤ簡 45nm 宸ヨ棟鍒堕�狅紝鍏锋湁杓冮珮鐨勬�ц兘鍔熻�楁瘮锛屽悓鏅傞泦鎴愪簡璞愬瘜鐨勯倧杓硣婧愬拰 DSP Slice锛岄仼鍚堜腑绛夊京闆滃害鐨勮ō瑷堥渶姹�銆�
绯诲垪锛歋partan-6
銆�銆�鍨嬭櫉锛歑C6SLX9-3FTG256I
銆�銆�灏佽锛欶TG256
銆�銆�閫熷害绛夌礆锛�-3
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master SelectMAP, etc.
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細9152
銆�銆�DSP Slice 鏁�(sh霉)閲忥細160
銆�銆�RAM 璩囨簮锛氱磩 270 Kb Distributed RAM 鍜� 1152 Kb Block RAM
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細174
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 85掳C锛�
XC6SLX9-3FTG256I 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘鑸囦綆鍔熻�楃殑绲愬悎锛氬熀浜� 45nm 宸ヨ棟鍒剁▼锛岃┎鑺墖鍦ㄤ繚璀夋�ц兘鐨勫悓鏅傞’钁楅檷浣庝簡鍔熻��銆�
銆�銆�2. 璞愬瘜鐨勯倧杓硣婧愶細鍖呭惈瓒呴亷 9000 鍊嬮倧杓柈鍏冿紝鑳藉婊胯冻澶氱ó鏁�(sh霉)瀛椾俊铏熻檿鐞嗙殑闇�姹�銆�
銆�銆�3. 鍏х疆 DSP Slice锛氭彁渚涘閬� 160 鍊� DSP Slice锛屾敮鎸侀珮鏁堝鐝�(xi脿n)涔樻硶鍣�銆佹烤娉㈠櫒浠ュ強鍏朵粬鏁�(sh霉)瀛搁亱绠楀姛鑳�銆�
銆�銆�4. 澶氱ó瀛樺劜璩囨簮锛氬収缃ぇ閲忓垎甯冨紡 RAM 鍜屽鐙� RAM锛屽彲浠ラ潏娲婚厤缃偤瀵勫瓨鍣�銆丗IFO 鎴栧叾浠栧瓨鍎茬祼妲�銆�
銆�銆�5. 鍙法绋� I/O锛氭敮鎸佸绋婧栨帴鍙ｅ崝(xi茅)璀帮紝渚嬪 PCIe銆丏DR3銆丩VDS 绛�锛岄仼鎳夋�у挤銆�
銆�銆�6. 闆嗘垚 DCI锛圖igital Clock Manager锛夛細鏀寔鏅傞悩鍊嶉牷銆佸垎闋讳互鍙婄浉浣嶈鏁寸瓑鍔熻兘锛屾彁鍗囩郴绲�(t菕ng)鏅傞悩绠＄悊鑳藉姏銆�
銆�銆�7. 鏀寔澶氱ó閰嶇疆妯″紡锛氬寘鎷緸 PROM 鍟熷嫊銆丣TAG 瑾胯│绛�锛屼究浜庨枊鐧�(f膩)鍜屾脯瑭�銆�
XC6SLX9-3FTG256I 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 宸ユキ(y猫)鑷嫊鍖栵細濡� PLC 鎺у埗鍣�銆佹鍣ㄤ汉鎺у埗绯荤当(t菕ng)绛�銆�
銆�銆�2. 娑堣不椤為浕瀛愮敘(ch菐n)鍝侊細濡傝闋昏檿鐞�銆侀煶闋荤法瑙ｇ⒓绛�銆�
銆�銆�3. 閫氫俊瑷倷锛氬灏忓瀷鍩虹珯銆佹暩(sh霉)鎿�(j霉)鍌宠几妯″绛夈��
銆�銆�4. 宓屽叆寮忕郴绲�(t菕ng)锛氬鍦栧儚铏曠悊銆佸偝鎰熷櫒鏁�(sh霉)鎿�(j霉)閲囬泦绛�銆�
銆�銆�5. 閱�(y墨)鐧傝ō鍌欙細濡傝秴鑱叉尝鍎�鍣�銆佺洠(ji膩n)璀峰剙绛夈��
銆�銆�鐢变簬鍏舵垚鏈晥鐩婇珮涓旇硣婧愯睈瀵�锛岄仼鐢ㄤ簬闇�瑕佷腑绛夎(gu墨)妯￠倧杓ō瑷堜絾灏嶆垚鏈晱鎰熺殑鎳夌敤鍫存櫙銆�
XC6SLX9-2FTG256C
銆�銆�XC6SLX9-3CSG324C
銆�銆�XC6SLX9-3CSG484C
