XC6SLX75T-2CSG484I 鏅傞枔锛�2025/4/29 10:03:00 闁辫畝锛�29

XC6SLX75T-2CSG484I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Spartan-6 绯诲垪 FPGA 鑺墖涓殑涓€鍊嬪瀷铏�銆係partan-6 FPGA 闈㈠悜浣庢垚鏈拰浣庡姛鑰楁噳(y墨ng)鐢紝寤ｆ硾閬╃敤浜庢秷璨�(f猫i)闆诲瓙銆侀€氫俊銆佸伐妤�(y猫)鎺у埗绛夐牁(l菒ng)鍩�銆傝┎鑺墖閲囩敤 45nm 宸ヨ棟鍒堕€�锛屽叿鍌欓珮鎬у児姣斿拰璞愬瘜鐨勯倧杓硣婧愶紝鏀寔澶氱ó宓屽叆寮忚檿鐞嗗拰淇¤櫉铏曠悊浠诲嫏(w霉)銆�
銆€銆€XC6SLX75T 鏄� Spartan-6 LX 绯诲垪涓殑涓€鍝★紝鍏锋湁杓冮珮鐨勯倧杓柈鍏冨瘑搴﹀拰璞愬瘜鐨� I/O 鎺ュ彛锛岄仼鍚堥渶瑕佽純楂樻€ц兘浣嗘垚鏈晱鎰熺殑鎳�(y墨ng)鐢ㄥ牬鏅€�

鍙冩暩(sh霉)

鍨嬭櫉锛歑C6SLX75T-2CSG484I
銆€銆€绯诲垪锛歋partan-6
銆€銆€灏佽锛欳SG484
銆€銆€閫熷害绛夌礆锛�-2
銆€銆€閰嶇疆闁冨瓨锛氫笉闆嗘垚
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細75K
銆€銆€RAM 瀹归噺锛�139Kb
銆€銆€DSP Slice 鏁�(sh霉)閲忥細160鍊�
銆€銆€I/O 鏁�(sh霉)閲忥細334鍊�
銆€銆€宸ヤ綔闆诲锛�1.2V 鏍稿績闆诲锛�1.5V/1.8V/2.5V/3.3V I/O 闆诲
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C 鍟嗘キ(y猫)绱�

鐗规€�

XC6SLX75T-2CSG484I 鎻愪緵浜嗛珮搴﹂潏娲荤殑鍙法绋嬮倧杓硣婧�锛屽叾涓昏鐗规€у寘鎷細
銆€銆€1. 楂樻€ц兘閭忚集绲�(ji茅)妲�(g貌u)锛氬熀浜庢煡鎵捐〃锛圠UT锛夌殑鏋舵(g貌u)锛屾彁渚涢珮閬�(d谩) 75,000 鍊嬮倧杓柈鍏�锛屾敮鎸佸京(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�(w霉)銆�
銆€銆€2. 宓屽叆寮忓瓨鍎插櫒濉婏細鍏�(n猫i)缃� 139Kb 鐨� Block RAM锛屽彲鐢ㄤ簬鏁�(sh霉)鎿�(j霉)绶╂矕銆丗IFO 鍜屽叾浠栧瓨鍎查渶姹�銆�
銆€銆€3. DSP Slice 鏀寔锛氬寘鍚� 160 鍊� DSP Slice锛岃兘澶犲姞閫熶箻娉曠疮鍔犵瓑閬�(y霉n)绠�锛岄仼鍚堥煶闋�銆佽闋诲拰閫氫俊闋�(l菒ng)鍩熴€�
銆€銆€4. 澶氭ǎ鍖栫殑 I/O 閰嶇疆锛氭敮鎸佸绋(bi膩o)婧�(zh菙n)鎺ュ彛鍗�(xi茅)璀�锛屽 PCIe銆丏DR2/3銆丩VDS 绛夛紝婊胯冻涓嶅悓鎳�(y墨ng)鐢ㄥ牬鏅殑闇€姹�銆�
銆€銆€5. 鍏�(n猫i)閮ㄦ檪閻樼鐞嗭細闆嗘垚 PLL 鍜� DCM 妯″锛屽彲鐢熸垚绮剧⒑鐨勬檪閻樹俊铏熶互椹�(q奴)鍕曞収(n猫i)閮ㄩ倧杓�銆�
銆€銆€6. 鍙潬鎬ц垏浣庡姛鑰楋細閲囩敤鍏堥€�(j矛n)鐨� 45nm 宸ヨ棟鍒剁▼锛屽叿鍌欏嫊鎱�(t脿i)鍔熻€楄(di脿o)绡€(ji茅)鍔熻兘锛岄檷浣庢暣楂旂郴绲�(t菕ng)鑳借€�銆�
銆€銆€7. 鏄撲簬浣跨敤鐨勮ō(sh猫)瑷堝伐鍏凤細鏀寔 Xilinx ISE Design Suite 鎴� Vivado Design Suite锛岀啊鍖栭枊鐧�(f膩)娴佺▼銆�

鎳�(y墨ng)鐢�

瑭茶姱鐗囬仼鐢ㄤ簬澶氱ó琛屾キ(y猫)鍜岄牁(l菒ng)鍩燂紝鍏稿瀷鎳�(y墨ng)鐢ㄥ寘鎷細
銆€銆€1. 瑕栭牷鍜屽湒鍍忚檿鐞嗭細渚嬪楂樻竻鏀濆儚姗�(j墨)銆侀’绀哄櫒鎺у埗鍣ㄧ瓑銆�
銆€銆€2. 閫氫俊瑷�(sh猫)鍌欙細濡傚皬鍨嬪熀绔�銆佺恫(w菐ng)绲�(lu貌)浜ゆ彌姗�(j墨)銆佽矾鐢卞櫒绛�銆�
銆€銆€3. 宸ユキ(y猫)鑷嫊鍖栵細閬�(y霉n)鍕曟帶鍒跺櫒銆丳LC銆佷汉姗�(j墨)鐣岄潰 (HMI) 绛�銆�
銆€銆€4. 娑堣不(f猫i)椤為浕瀛愮敘(ch菐n)鍝侊細澶氬獟楂旀挱鏀惧櫒銆佹父鎴叉(j墨)閰嶄欢绛�銆�
銆€銆€5. 閱�(y墨)鐧傝ō(sh猫)鍌欙細瓒呰伈娉㈣ō(sh猫)鍌欍€佷究鏀滃紡瑷烘柗鍎€鍣ㄧ瓑銆�
銆€銆€6. 宓屽叆寮忚▓绠楀钩鑷猴細浣滅偤鍗�(xi茅)铏曠悊鍣ㄦ垨涓绘帶鍠厓閬�(y霉n)琛屽鏅傛搷浣滅郴绲�(t菕ng)銆�