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XC6SLX75-3FG676I 鏄� Xilinx 鍏徃 Spartan-6 绯诲垪 FPGA 鐨勪竴绋瀷铏�銆係partan-6 绯诲垪 FPGA 鎻愪緵楂樻�ц兘銆佷綆鍔熻�楃殑瑙ｆ焙鏂规锛岄仼鐢ㄤ簬鍚勭ó宓屽叆寮忔噳鐢ㄥ拰閫氫俊绯荤当(t菕ng)銆傝┎鍣ㄤ欢鍩轰簬鎴愮啛鐨� 45nm 宸ヨ棟鎶�琛撳埗閫�锛屽叿鏈夎睈瀵岀殑閭忚集璩囨簮銆佸祵鍏ュ紡濉婂瓨鍎插櫒銆丏SP Slice 鍜屽叾浠栧皥鐢ㄧ‖浠舵ā濉�銆�
銆�銆�Spartan-6 FPGA 闈炲父閬╁悎闇�瑕侀珮鎬у児姣旂殑鎳夌敤鍫存櫙锛屼緥濡傚伐妤�(y猫)鎺у埗銆佹苯杌婇浕瀛�銆佹秷璨婚闆诲瓙鐢㈠搧绛夈�傛澶栵紝瀹冮倓鏀寔澶氱ó鎺ュ彛妯欐簴锛屽寘鎷� PCIe銆丏DR3 鍜屽崈鍏嗕互澶恫绛�銆�
鍨嬭櫉锛歑C6SLX75
銆�銆�绯诲垪锛歋partan-6
銆�銆�宸ヨ棟锛�45nm
銆�銆�閰嶇疆妯″紡锛歋lave Serial
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�I/O 鏁�(sh霉)閲忥細416
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏ч儴闁冨瓨锛岄渶澶栨帴閰嶇疆鑺墖
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細75K
銆�銆�Block RAM锛�2.4Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細160
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銆�銆�1. 楂樻�ц兘鏋舵锛氶噰鐢ㄥ叐灞や簰鑱�(li谩n)绲愭锛屾敮鎸侀珮閬� 500 MHz 鐨勬檪閻橀牷鐜�銆�
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銆�銆�5. 鍏х疆纭牳妯″锛氶泦鎴� SelectIO 鎶�琛撱�丏CM锛堟暩(sh霉)瀛楁檪閻樼鐞嗗櫒锛変互鍙� GTP 鏀剁櫦(f膩)鍣紙閮ㄥ垎鍨嬭櫉鏀寔锛�銆�
銆�銆�6. 鍔熻�楀劒(y艒u)鍖栵細鎻愪緵 PowerPC 鎶�琛撲互闄嶄綆鍕曟厠(t脿i)鍔熻��锛屽苟鏀寔澶氶浕澹撲緵闆绘柟妗�銆�
銆�銆�7. 瀹夊叏鎬э細鏀寔 AES 鍜� RSA 鍔犲瘑绠楁硶锛屼繚璀风敤鎴惰ō瑷堢殑鐭ヨ瓨鐢㈡瑠銆�
XC6SLX75-3FG676I 寤ｆ硾鎳夌敤浜庡鍊嬮牁鍩�锛屽寘鎷絾涓嶉檺浜庝互涓嬫柟闈細
銆�銆�1. 宸ユキ(y猫)鑷嫊鍖栵細濡� PLC 鎺у埗鍣�銆侀亱鍕曟帶鍒跺櫒鍜� CNC 姗熷簥涓殑鏁�(sh霉)鎿�(j霉)铏曠悊鑸囧鏅傛帶鍒躲��
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銆�銆�3. 閫氫俊瑷倷锛氶仼鐢ㄤ簬鍩虹珯鏀剁櫦(f膩)淇℃銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑淇¤櫉铏曠悊浠诲嫏銆�
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XC6SLX75T-3FGG676I
