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XC6SLX45T-4CSG484C 鏄� Xilinx 鍏徃 Spartan-6 绯诲垪 FPGA 鐨勪竴绋瀷铏�锛岄噰鐢� 484 寮曡叧 CSG 灏佽銆係partan-6 绯诲垪浠ュ叾楂樻�у児姣斿拰浣庡姛鑰楄ō瑷堣憲绋�锛岄仼鐢ㄤ簬宸ユキ(y猫)鎺у埗銆侀�氫俊銆佹秷璨婚浕瀛愪互鍙婇啱(y墨)鐧傝ō鍌欑瓑闋�(l菒ng)鍩�銆�
銆�銆�Spartan-6 鍣ㄤ欢鍩轰簬鎴愮啛鐨� 45nm 宸ヨ棟鎶�琛�(sh霉)鍒堕�狅紝闆嗘垚浜嗗彲绶ㄧ▼閭忚集璩囨簮銆佸祵鍏ュ紡濉婂瓨鍎插櫒銆丏SP Slice 鍜屽皥鐢� I/O 妯″绛夌祫浠�銆傝┎绯诲垪鏀寔澶氱ó楂樻�ц兘鎺ュ彛妯欐簴锛屽苟涓旈�氶亷闈堟椿鐨勬灦妲�(g貌u)婊胯冻澶氭ǎ鍖栫殑瑷▓闇�姹�銆�
鍣ㄤ欢鍨嬭櫉锛歑C6SLX45T-4CSG484C
銆�銆�灏佽椤炲瀷锛欳SG484
銆�銆�閫熷害绛夌礆锛�-4
銆�銆�FPGA 绯诲垪锛歋partan-6
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 28800 鍊� slice
銆�銆�閰嶇疆闁冨瓨锛氫笉闆嗘垚
銆�銆�鏈�澶х敤鎴� I/O 鏁�(sh霉)閲忥細314
銆�銆�鍏�(n猫i)閮� RAM 瀹归噺锛氱磩 576 KB (鍒嗗竷寮� RAM 鍜屽 RAM)
銆�銆�DSP Slice 鏁�(sh霉)閲忥細180
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 90掳C锛�
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹� 1.2V锛孖/O 闆诲 1.8V/2.5V/3.3V
XC6SLX45T-4CSG484C 鎻愪緵浜嗚睈瀵岀殑纭欢璩囨簮鍜岄潏娲荤殑鏋舵(g貌u)鍔熻兘锛�
銆�銆�1. 楂樻�ц兘閭忚集鏋舵(g貌u)锛氭瘡鍊� CLB锛圕onfigurable Logic Block锛夊寘鍚叐鍊嬬崹绔嬬殑 Slice锛岃兘澶�?q奴)宕縁(xi脿n)楂樻晥鐨勭祫鍚堝拰鏅傚簭閭忚集鎿嶄綔銆�
銆�銆�2. 鍏�(n猫i)閮ㄥ瓨鍎插櫒锛氬寘鎷垎甯冨紡 RAM 鍜屽閬� 180Kb 鐨勫 RAM锛岄仼鍚堢敤浜庢暩(sh霉)鎿�(j霉)绶╁瓨銆丗IFO 鎴栨煡鎵捐〃绛夊姛鑳�銆�
銆�銆�3. DSP 鏀寔锛氬収(n猫i)缃� DSP48A1 Slice锛屽叿鏈� 25x18 浣嶄箻娉曞櫒鍜� 48 浣嶅姞娉�/娓涙硶鍣�锛屽唬娉涙噳鐢ㄤ簬鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�銆�
銆�銆�4. 鍙厤缃� I/O锛氭敮鎸佸绋婧栧 LVCMOS銆丩VDS 鍜� SelectIO锛屾柟渚块�ｆ帴澶栭儴瑷倷銆�
銆�銆�5. 鍏�(n猫i)缃檪閻樼鐞嗘ā濉婏細鏀寔 PLL 鍜� DCM锛屾彁渚涚簿纰虹殑鏅傞悩鍒嗛牷銆佸�嶉牷鍜岀浉绉诲姛鑳姐��
銆�銆�6. 鍔熻�楀劒(y艒u)鍖栵細閲囩敤 Power-on 榛樿獚鐙�鎱�(t脿i)瑷疆鍜屽嫊鎱�(t脿i)鍔熻�楄(di脿o)绡�(ji茅)鎶�琛�(sh霉)锛屾湁鏁堥檷浣庣郴绲�(t菕ng)鑳借��銆�
銆�銆�7. 蹇�熷暉鍕曟檪闁擄細浣跨敤灏堢敤閰嶇疆寮曡叧鎴栧鎺� SPI Flash 瀵︾従(xi脿n)蹇�熷姞杓夋瘮鐗规祦鏂囦欢銆�
XC6SLX45T-4CSG484C 鍦ㄤ互涓嬮牁(l菒ng)鍩熸湁寤ｆ硾鎳夌敤锛�
銆�銆�1. 宸ユキ(y猫)鑷嫊鍖栵細瀵︽檪鎺у埗銆侀亱鍕曟帶鍒�銆佸偝鎰熷櫒鏁�(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞嗐��
銆�銆�2. 閫氫俊瑷倷锛氬熀甯朵俊铏熻檿鐞�銆佸崝(xi茅)璀拌綁(zhu菐n)鎻�銆佹暩(sh霉)鎿�(j霉)鍖呭垎椤炶垏杞�(zhu菐n)鐧�(f膩)銆�
銆�銆�3. 娑堣不椤為浕瀛愮敘(ch菐n)鍝侊細瑕栭牷鍦栧儚铏曠悊銆侀煶闋昏В纰艰垏澧炲挤銆�
銆�銆�4. 閱�(y墨)鐧傚剙鍣細瓒呰伈娉㈡垚鍍�銆佸績闆诲湒鍒嗘瀽銆佹偅鑰呯洠(ji膩n)璀风郴绲�(t菕ng)銆�
銆�銆�5. 娓│娓噺锛氱ず娉㈠櫒瑙哥櫦(f膩)閭忚集銆佷换鎰忔尝褰㈢敓鎴愩�侀珮閫熸暩(sh霉)鎿�(j霉)閲囬泦銆�
銆�銆�6. 鑸┖鑸ぉ鑸囧湅闃诧細灏庤埅绯荤当(t菕ng)銆侀浄閬斾俊铏熻檿鐞嗐�佸姞瀵嗛�氫俊妯″銆�
XC6SLX45T-3CSG484C
銆�銆�XC6SLX45T-2CSG484C
