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XC6SLX45T-3CSG484I 鏄� Xilinx 鍏徃 Spartan-6 绯诲垪 FPGA 涓殑涓�娆惧叿楂斿瀷铏�銆傝┎绯诲垪 FPGA 鎻愪緵浜嗛珮鎬ц兘銆佷綆鍔熻�楃殑瑙ｆ焙鏂规锛岄仼鐢ㄤ簬鍚勭ó宸ユキ(y猫)銆侀�氫俊鍜屾秷璨婚鎳夌敤銆係partan-6 鍩轰簬 45nm 宸ヨ棟鎶�琛撳埗閫�锛屾彁渚涜睈瀵岀殑閭忚集璩囨簮銆佸祵鍏ュ紡濉� RAM 鍜� DSP 妯″銆�
銆�銆�Spartan-6 FPGA 鍖呮嫭鍏╁�嬫灦妲嬮鍨嬶細闈炴槗澶辨�ч厤缃殑 Spartan-6 LX 鍜岄泦鎴愪簡娣峰悎妯″紡 ADC 鐨� Spartan-6 LXT銆俋C6SLX45T 灞簬 Spartan-6 LX 绯诲垪锛屽叿鏈夐珮鎬у児姣旂殑鐗归粸锛岄仼鍚堥渶瑕佷腑绛夐倧杓瘑搴﹀拰浣庡姛鑰楃殑鎳夌敤鍫存櫙銆�
鍨嬭櫉锛歑C6SLX45T-3CSG484I
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歋partan-6
銆�銆�宸ヨ棟鍒剁▼锛�45nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 27,168 鍊� CLB锛堝彲閰嶇疆閭忚集濉婏級
銆�銆�RAM 璩囨簮锛氱磩 1.4Mb 宓屽叆寮忓 RAM
銆�銆�DSP Slice 鏁�(sh霉)閲忥細90 鍊�
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細326 鍊�
銆�銆�灏佽椤炲瀷锛欳SG484锛�484 寮曡叧闄剁摲 Quad Flatpack锛�
銆�銆�閫熷害绛夌礆锛�-3锛堣〃绀鸿純蹇殑閫熷害绛夌礆锛�
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 85掳C锛夋垨宸ユキ(y猫)绱氾紙-40掳C 鑷� 100掳C锛�锛屽叿楂斿彇姹轰簬瑷傝臣閬搁爡
XC6SLX45T-3CSG484I 鍏锋湁浠ヤ笅涓昏鐗规�э細
銆�銆�1. 楂樻�ц兘鏋舵锛氬熀浜庡叐闅庢娴佹按绶� CLB 瑷▓锛屾敮鎸佹洿楂樼殑閬嬭闋荤巼鍜屾檪閻橀�熺巼銆�
銆�銆�2. 鍏х疆瀛樺劜鍣ㄨ硣婧愶細鎻愪緵浜嗗ぇ閲忕殑鍒嗗竷寮� RAM 鍜屽 RAM锛屼究浜庡鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)鎿�(j霉)绶╂矕鍜屽瓨鍎插姛鑳�銆�
銆�銆�3. DSP 鍔熻兘锛氬寘鍚皥鐢ㄧ殑 DSP48A1 Slice锛屽彲浠ラ珮鏁堝畬鎴愪箻娉曠疮鍔犵瓑閬嬬畻浠诲嫏锛岄潪甯搁仼鍚堟暩(sh霉)瀛椾俊铏熻檿鐞嗘噳鐢ㄣ��
銆�銆�4. 鍙法绋� I/O锛氭敮鎸佸绋婧栨帴鍙ｅ崝(xi茅)璀�锛屽寘鎷� PCIe銆佸崈鍏嗕互澶恫(w菐ng)銆乁SB 绛�銆�
銆�銆�5. 浣庡姛鑰楄ō瑷堬細閲囩敤 Power-on-the-Fly 鎶�琛擄紝鍕曟厠(t脿i)瑾挎暣宸ヤ綔闆诲鍜岄牷鐜囦互鍎�(y艒u)鍖栧姛鑰�銆�
銆�銆�6. 鏄撶敤鎬у挤锛氶�氶亷 Xilinx ISE 鎴� Vivado 宸ュ叿閺堥�茶瑷▓闁嬬櫦(f膩)锛屾敮鎸� HDL 鍜� IP 鏍搁泦鎴愩��
銆�銆�7. 寤ｆ硾鐨勬噳鐢ㄥ牬鏅細閬╃敤浜庨�氫俊鍩虹瑷柦銆佸湒鍍忚檿鐞嗐�佸伐妤�(y猫)鎺у埗銆侀啱(y墨)鐧傝ō鍌欑瓑闋樺煙銆�
XC6SLX45T-3CSG484I 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊绯荤当(t菕ng)锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙涓殑鏁�(sh霉)鎿�(j霉)鍖呰檿鐞嗘ā濉娿��
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鐢ㄤ簬瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮枫�佸鏅傚垎鏋愮瓑鍔熻兘銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細鍦ㄩ亱鍕曟帶鍒躲�佹鍣ㄤ汉瑕栬銆佸偝鎰熷櫒铻嶅悎绛夋柟闈㈢櫦(f膩)鎻噸瑕佷綔鐢�銆�
銆�銆�4. 閱�(y墨)鐧傞浕瀛愶細渚嬪瓒呰伈娉㈣ō鍌欍�佹牳纾佸叡鎸垚鍍忎腑鐨勪俊铏熼噰闆嗚垏铏曠悊銆�
銆�銆�5. 娑堣不椤為浕瀛愮敘鍝侊細娓告埐姗�銆侀珮娓呴浕瑕栦腑鐨勫湒褰㈡覆鏌撳拰澶氬獟楂旇檿鐞�銆�
銆�銆�6. 姹借粖闆诲瓙锛氶珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛圓DAS锛夈�佽粖杓変俊鎭妯傜郴绲�(t菕ng)鐨勭‖浠跺姞閫熼儴鍒�銆�
XC6SLX45T-2CSG484C
銆�銆�XC6SLX45T-3FTG256I
銆�銆�XC6SLX45T-3CPGA484I
