XC6SLX45-N3FGG484I 鏅�(sh铆)闁擄細2025/4/29 14:53:22 闁辫畝锛�28

XC6SLX45-N3FGG484I 鏄� Xilinx 鍏徃 Spartan-6 绯诲垪 FPGA 鐨勪竴绋瀷铏�(h脿o)銆係partan-6 FPGA 闈㈠悜浣庢垚鏈�銆佷綆鍔熻€楁噳(y墨ng)鐢ㄨō(sh猫)瑷�(j矛)锛岄仼鐢ㄤ簬鍚勭ó宸ユキ(y猫)銆侀€氫俊鍜屾秷璨�(f猫i)椤�(l猫i)闆诲瓙闋�(l菒ng)鍩�銆傝┎绯诲垪鍩轰簬 45nm 宸ヨ棟鎶€琛�(sh霉)锛屾彁渚涗簡璞愬瘜鐨勯倧杓硣婧�銆佸祵鍏ュ紡瀛樺劜(ch菙)鍣ㄥ鍜� DSP 濉�锛屾敮鎸侀潏娲荤殑 I/O 妯�(bi膩o)婧�(zh菙n)閰嶇疆銆�
銆€銆€XC6SLX45 鏄� Spartan-6 绯诲垪涓殑涓瓑瑕�(gu墨)妯″櫒浠�锛屽叿鏈夎壇濂界殑鎬�?x煤n)r(ji脿)姣�锛岄仼鍚堥渶瑕佷竴瀹氶倧杓京(f霉)闆滃害浣嗗皪(du矛)鎴愭湰鏁忔劅鐨勬噳(y墨ng)鐢ㄥ牬(ch菐ng)鏅€�

鍙冩暩(sh霉)

閭忚集鍠厓锛圫lice锛夛細27,168
銆€銆€Block RAM锛�1,080 Kb
銆€銆€DSP Slice锛�120
銆€銆€I/O 鏁�(sh霉)閲忥細332
銆€銆€閰嶇疆妯″紡锛歋electMAP銆丮aster SPI銆丼lave SPI銆丅oundary Scan
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆€銆€灏佽椤�(l猫i)鍨嬶細FGG484
銆€銆€鏍稿績闆诲锛�1.2V
銆€銆€I/O 闆诲锛�1.8V銆�2.5V銆�3.3V

鐗规€�

XC6SLX45-N3FGG484I 鎻愪緵浜嗛珮鎬ц兘鐨勯倧杓檿鐞嗚兘鍔涳紝鍚屾檪(sh铆)鍏奸¨浜嗕綆鍔熻€楃壒鎬�銆傚叾鍏�(n猫i)閮ㄦ灦妲�(g貌u)鍖呮嫭鍙法绋嬮倧杓锛圕LB锛夈€佸垎甯冨紡 RAM銆丅lock RAM 鍜� DSP Slice锛岃兘澶�?q奴)宕縁(xi脿n)寰�(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏�(h脿o)铏曠悊鍔熻兘銆�
銆€銆€瑭茶姱鐗囬倓闆嗘垚浜嗗绋‖鏍告ā濉�锛屼緥濡傛檪(sh铆)閻樼鐞嗗柈鍏冿紙DCM 鍜� PLL锛�锛屼互鍙婂皥(zhu膩n)鐢ㄧ殑閰嶇疆鍜岃(di脿o)瑭︽帴鍙ｃ€�
銆€銆€Spartan-6 绯诲垪 FPGA 鐨勪竴澶х壒榛�(di菐n)鏄叾鍓�(chu脿ng)鏂扮殑鍏╃礆(j铆)浜掕伅(li谩n)鏋舵(g貌u)锛屽寘鎷� Switch Matrix 鍜� Dedicated Interconnect锛岄€欑ó绲�(ji茅)妲�(g貌u)鎻愰珮浜嗘€ц兘骞堕檷浣庝簡寤堕伈銆�
銆€銆€姝ゅ锛孹C6SLX45 鏀寔澶氱ó宸ユキ(y猫)妯�(bi膩o)婧�(zh菙n)鎺ュ彛鍗�(xi茅)璀�锛屽 PCIe銆丏DR3銆佸崈鍏嗕互澶恫(w菐ng)绛�锛岄潪甯搁仼鍚堥€氫俊銆佽闋昏檿鐞嗗拰宓屽叆寮忔帶鍒剁瓑鎳�(y墨ng)鐢ㄥ牬(ch菐ng)鏅€�

鎳�(y墨ng)鐢�

XC6SLX45-N3FGG484I 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆€銆€1. 宸ユキ(y猫)鑷嫊(d貌ng)鍖栬垏鎺у埗锛氱敤浜庢暩(sh霉)鎿�(j霉)閲囬泦銆侀亱(y霉n)鍕�(d貌ng)鎺у埗銆佸湒鍍忚檿鐞嗙瓑浠诲嫏(w霉)銆�
銆€銆€2. 閫氫俊瑷�(sh猫)鍌欙細閬╃敤浜庣劇(w煤)绶�(xi脿n)鍩虹珯銆佺恫(w菐ng)绲�(lu貌)浜ゆ彌姗�(j墨)鍜屽叾浠栭€氫俊鍩虹(ch菙)瑷�(sh猫)鏂�銆�
銆€銆€3. 娑堣不(f猫i)椤�(l猫i)闆诲瓙鐢�(ch菐n)鍝侊細濡傞珮娓呰闋昏檿鐞嗐€佹暩(sh霉)纰肩浉姗�(j墨)銆佹父鎴叉(j墨)绛�銆�
銆€銆€4. 閱�(y墨)鐧傝ō(sh猫)鍌欙細濡傝秴鑱叉尝鎴愬儚銆佹偅鑰呯洠(ji膩n)璀�(h霉)绯荤当(t菕ng)绛�銆�
銆€銆€5. 杌�(ch膿)杓夐浕瀛愶細鐢ㄤ簬椐曢杓斿姪绯荤当(t菕ng)銆佽粖(ch膿)杓変俊鎭妯�(l猫)绯荤当(t菕ng)绛�銆�
銆€銆€瑭� FPGA 閭勮鐢ㄤ綔鍘熷瀷椹�(y脿n)璀夊钩鑷�(t谩i)锛屽湪 ASIC 瑷�(sh猫)瑷�(j矛)鍒濇湡鎻愪緵蹇€熻凯浠ｈ兘鍔�銆�