鏅傞枔锛�2025/5/7 15:12:51
闁辫畝锛�27
XC6SLX45-N3FGG484C 鏄� Xilinx 鍏徃 Spartan-6 绯诲垪 FPGA 鐨勪竴鍊嬪瀷铏�銆傝┎鍣ㄤ欢閲囩敤 45nm 宸ヨ棟鎶�琛撳埗閫�锛屽叿鍌欒睈瀵岀殑閭忚集璩囨簮銆佸祵鍏ュ紡濉婂瓨鍎插櫒鍜� DSP 妯″锛岄仼鐢ㄤ簬澶氱ó鏁稿瓧淇¤櫉铏曠悊鍜屾帶鍒舵噳鐢�銆係partan-6 绯诲垪浠ュ叾楂樻�у児姣斿拰浣庡姛鑰楄�岃仦鍚嶏紝寤ｆ硾鎳夌敤浜庡伐妤�(y猫)銆侀�氫俊銆佹秷璨婚浕瀛愬拰姹借粖闋樺煙銆�
銆�銆�姝ゅ瀷铏熷叿鏈� -N3 閫熷害绛夌礆锛屽苟閲囩敤 FGG484 灏佽锛屾敮鎸佸閬� 484 鍊嬪紩鑵�銆傚畠闈炲父閬╁悎闇�瑕侀珮鎬ц兘鑸囬潏娲绘�х殑鎳夌敤鍫存櫙銆�
鍨嬭櫉锛歑C6SLX45-N3FGG484C
銆�銆�绯诲垪锛歋partan-6
銆�銆�鍝佺墝锛歑ilinx
銆�銆�灏佽锛欶GG484
銆�銆�閫熷害绛夌礆锛�-N3
銆�銆�閭忚集鍠厓鏁搁噺锛氱磩 45,000 鍊�
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏х疆閰嶇疆闁冨瓨锛堥渶澶栨帴閰嶇疆 PROM锛�
銆�銆�RAM 瀹归噺锛�576 KB
銆�銆�DSP 妯″鏁搁噺锛�120 鍊�
銆�銆�I/O 鏁搁噺锛�336 鍊�
銆�銆�鏈�澶у伐浣滈牷鐜囷細楂橀仈 379 MHz
銆�銆�闆绘簮闆诲锛氭牳蹇冮浕澹� 1.2V锛孖/O 闆诲鏀寔 1.2V/1.5V/1.8V/2.5V/3.3V
銆�銆�宸ヨ棟绡�(ji茅)榛烇細45nm
銆�銆�婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 70掳C锛�
XC6SLX45-N3FGG484C 鎻愪緵浜嗗挤澶х殑鍙法绋嬮倧杓兘鍔涳紝鑳藉闈堟椿瀵︾従(xi脿n)鍚勭ó寰╅洔鐨勬暩瀛楅浕璺ō瑷�銆傚叾闂滈嵉鐗规�у寘鎷細
銆�銆�1. 楂樻�ц兘閭忚集绲愭锛氬熀浜庢煡鎵捐〃 (LUT) 鐨勬灦妲�锛屾彁渚涢珮鏁堢殑閭忚集瀵嗗害鍜屾�ц兘銆�
銆�銆�2. 鍏х疆瀛樺劜鍣ㄦā濉婏細姣忓�� CLB锛圕onfigurable Logic Block锛夊寘鍚鍊嬪垎甯冨紡 RAM 鍜屽鐙� RAM 璩囨簮锛岀附瑷� 576 KB 鐨勫瓨鍎插閲�銆�
銆�銆�3. DSP Slice 鏀寔锛氶泦鎴愪簡灏堢敤鐨勪箻娉曞櫒绱姞鍣ㄦā濉�锛岀敤浜庡姞閫熸暩瀛椾俊铏熻檿鐞嗕换鍕欍��
銆�銆�4. 闆欓�氶亾 SelectMAP 鍜屽柈閫氶亾 Slave Serial 閰嶇疆鎺ュ彛锛屼究浜庨�氶亷澶栭儴 PROM 鎴� MCU 鍔犺級閰嶇疆鏁告摎銆�
銆�銆�5. 鏀寔澶氱ó I/O 妯欐簴锛屽寘鎷� LVCMOS銆丩VDS 鍜� SSTL 绛�锛岄仼鍚堝唬娉涚殑鎺ュ彛闇�姹�銆�
銆�銆�6. 鍏х疆鏅傞悩绠＄悊妯″ DCM 鍜� PLL锛屽彲鐢熸垚绮炬簴鐨勬檪閻樹俊铏熷苟閫茶鐩镐綅瑾挎暣銆�
銆�銆�7. 鐗囦笂瑾胯│鍔熻兘锛氭敮鎸� Chipscope 鍜� JTAG 鎺ュ彛锛屼究浜庡湪绶氳瑭﹀拰鍒嗘瀽绯荤当(t菕ng)琛岀偤銆�
XC6SLX45-N3FGG484C 鍦ㄨū澶氶牁鍩熼兘鏈夊唬娉涙噳鐢紝鍏稿瀷鎳夌敤鍫存櫙鍖呮嫭锛�
銆�銆�1. 宸ユキ(y猫)鑷嫊鍖栬ō鍌欎腑鐨勫鏅傛帶鍒跺拰鏁告摎閲囬泦銆�
銆�銆�2. 閫氫俊绯荤当(t菕ng)涓殑鍗�(xi茅)璀拌綁鎻�銆佷俊铏熻鍒惰В瑾垮拰鏁告摎璺敱銆�
銆�銆�3. 瑕栭牷鍜屽湒鍍忚檿鐞�锛屼緥濡傞珮娓呰闋荤法纰艰В纰笺�佹牸寮忚綁鎻涗互鍙婅瑕烘娓�銆�
銆�銆�4. 閱�(y墨)鐧傚剙鍣ㄤ腑鐨勪俊铏熻檿鐞嗗拰娉㈠舰鐢熸垚銆�
銆�銆�5. 姹借粖闆诲瓙涓殑鍌虫劅鍣ㄨ瀺鍚堝拰淇℃伅椤ず銆�
銆�銆�6. 娑堣不椤為浕瀛愮敘鍝�锛屽澶氬獟楂旀挱鏀惧櫒鍜屾父鎴叉鐨勬牳蹇冩帶鍒跺柈鍏�銆�
銆�銆�姝ゅ锛岀敱浜庡叾闈堟椿鐨勭‖浠舵灦妲�锛岃┎ FPGA 閭勫彲鐢ㄤ簬蹇�熷師鍨嬮枊鐧�(f膩)鍜屽畾鍒� ASIC 鏇夸唬鏂规銆�
XC6SLX45T-2FGG484C, XC6SLX45-3FGG484C
