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鍨嬭櫉(h脿o)锛歑C6SLX4-L1CSG225I
銆€銆€绯诲垪锛歋partan-6
銆€銆€鍒堕€犲晢锛歑ilinx
銆€銆€宸ヨ棟绡€(ji茅)榛�(di菐n)锛�45nm
銆€銆€FPGA 閭忚集鍠厓鏁�(sh霉)锛�4,224 CLB Slices
銆€銆€閰嶇疆妯″紡锛歁aster SPI
銆€銆€瀛樺劜(ch菙)鍣細90Kb Distributed RAM锛�216Kb Block RAM
銆€銆€DSP Slice 鏁�(sh霉)閲忥細80鍊�(g猫)
銆€銆€I/O 寮曡叧鏁�(sh霉)閲忥細156鍊�(g猫)
銆€銆€灏佽椤炲瀷锛欳SG (Fine-Pitch BGA)
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆€銆€渚涢浕闆诲锛欳ore VCCINT=1.2V锛孖/O VCCO=1.8V/2.5V/3.3V

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