鏅傞枔锛�2025/5/7 13:07:17
闁辫畝锛�21
XC6SLX25T-N3FGG484I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Spartan-6 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏熴�係partan-6 绯诲垪浠ュ叾楂樻�у児姣斿拰璞愬瘜鐨勫姛鑳借硣婧愯�岃憲绋�锛岄仼鐢ㄤ簬鍚勭ó涓綆瀵嗗害鐨勯倧杓ō瑷堛�佸祵鍏ュ紡铏曠悊浠ュ強閫氫俊鎳夌敤銆傝┎鑺墖閲囩敤 45nm 宸ヨ棟鍒堕�狅紝鍏峰倷寮峰ぇ鐨勬�ц兘鑸囪純浣庣殑鍔熻��锛屽悓鏅傛敮鎸佸绋厤缃伕闋呬互婊胯冻涓嶅悓鎳夌敤鍫存櫙鐨勯渶姹傘��
銆�銆�瑭插瀷铏熺殑鍏烽珨灏佽鐐� FGG484锛屽伐浣滄韩搴﹁寖鍦嶇鍚堝伐妤�(y猫)妯欐簴锛岄仼鍚堝湪杓冪偤鑻涘埢鐨勭挵(hu谩n)澧冧笅閬嬭銆�
鍨嬭櫉锛歑C6SLX25T-N3FGG484I
銆�銆�绯诲垪锛歋partan-6
銆�銆�鍝佺墝锛歑ilinx
銆�銆�宸ヨ棟锛�45nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細24976
銆�銆�RAM 瀹归噺锛�120KB
銆�銆�DSP Slice 鏁�(sh霉)閲忥細56
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�334
銆�銆�閰嶇疆妯″紡锛氬緸 SPI 鎴� BPI 闁冨瓨鍟熷嫊
銆�銆�宸ヤ綔闆诲锛�1.2V 鏍稿績闆诲锛�3.3V I/O 闆诲
銆�銆�灏佽锛欶GG484
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XC6SLX25T-N3FGG484I 鎻愪緵浜嗚睈瀵岀殑纭欢璩囨簮锛屽寘鎷ぇ閲忕殑鍙法绋嬮倧杓柈鍏�銆佸 RAM锛圔lock RAM锛夈�丏SP Slice 鍜屽皥鐢ㄧ殑纭牳妯″銆傞�欎簺鐗规�т娇鍏堕潪甯搁仼鍚堢敤浜庡京闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕欏拰瀵︽檪鎺у埗鎳夌敤銆�
銆�銆�1. 鍙法绋嬮倧杓硣婧愯睈瀵�锛屾敮鎸佸鐝�(xi脿n)寰╅洔鐨勭祫鍚堥倧杓拰鏅傚簭閭忚集闆昏矾銆�
銆�銆�2. 鍏х疆 Block RAM 妯″锛屽彲浠ョ敤浜庢暩(sh霉)鎿氱珐瀛�銆佹煡鎵捐〃鎴� FIFO 绶╂矕绛夊姛鑳�銆�
銆�銆�3. DSP Slice 鎻愪緵浜嗛珮鏁堢殑涔樻硶绱姞閬嬬畻鑳藉姏锛岄仼鐢ㄤ簬闊抽牷銆佽闋诲拰鍏朵粬淇¤櫉铏曠悊绠楁硶銆�
銆�銆�4. 鏀寔澶氱ó鎺ュ彛鍗�(xi茅)璀帮紝濡� PCIe銆佸崈鍏嗕互澶恫 MAC 鍜� RocketIO 绛夐珮閫熶覆琛屾帴鍙ｃ��
銆�銆�5. 閰嶅倷闈堟椿鐨勬檪閻樼鐞嗗伐鍏凤紙Clock Management Tile, CMT锛�锛屾敮鎸� PLL 鍜� DCM 鍔熻兘锛岃兘澶犵敓鎴愮簿纰虹殑鏅傞悩淇¤櫉銆�
銆�銆�6. 鍏锋湁浣庡姛鑰楃壒鎬�锛屽挨鍏跺湪寰呮妯″紡涓嬪彲浠ラ’钁楅檷浣庤兘婧愭秷鑰椼��
銆�銆�7. 鎻愪緵澶氱ó閰嶇疆鏂瑰紡锛岀敤鎴跺彲浠ユ牴鎿氬叿楂旈渶姹傞伕鎿囨渶閬╁悎鐨勫暉鍕曟柟妗�銆�
鐢变簬 XC6SLX25T-N3FGG484I 鐨勫挤澶ф�ц兘鍜岄潏娲绘��锛屽畠琚唬娉涙噳鐢ㄤ簬澶氬�嬮牁鍩燂細
銆�銆�1. 宓屽叆寮忕郴绲�(t菕ng)闁嬬櫦(f膩)锛氫緥濡傚伐妤�(y猫)鎺у埗瑷倷銆佸鐢ㄩ浕鍣ㄦ帶鍒跺櫒绛�銆�
銆�銆�2. 閫氫俊鍩虹瑷柦锛氬灏忓瀷鍩虹珯銆佺劇绶氶�氫俊妯″銆�
銆�銆�3. 鍦栧儚铏曠悊鑸囪▓绠楁瑕栬锛氬彲鐢ㄤ簬瀹夐槻鏀濆儚闋殑鏁�(sh霉)鎿氶爯铏曠悊銆�
銆�銆�4. 閱�(y墨)鐧傝ō鍌欙細姣斿瓒呰伈娉㈣ō鍌�銆佸績闆诲湒鍒嗘瀽鍎�鍣�銆�
銆�銆�5. 娑堣不闆诲瓙锛氬楂樻竻闆昏銆佹父鎴叉澶栧湇瑷倷銆�
銆�銆�6. 姹借粖闆诲瓙锛氬杌婅級淇℃伅濞涙▊绯荤当(t菕ng)銆侀椐涜紨鍔╃郴绲�(t菕ng)涓殑鏁�(sh霉)鎿氳檿鐞嗗柈鍏�銆�
銆�銆�閫欐 FPGA 鐗瑰垾閬╁悎闇�瑕侀珮鎬ц兘瑷堢畻鑳藉姏鍜屽京闆滄帴鍙ｉ泦鎴愮殑鎳夌敤鍫存櫙銆�
XC6SLX25T-3FGG484C
銆�銆�XC6SLX25T-2FGG484C
