鏅傞枔锛�2025/5/12 13:17:12
闁辫畝锛�23
XC6SLX16-L1CSG324I 鏄� Xilinx 鍏徃 Spartan-6 绯诲垪 FPGA 鐨勪竴绋瀷铏熴�係partan-6 绯诲垪 FPGA 閲濆皪浣庢垚鏈拰浣庡姛鑰楃殑鎳夌敤閫茶浜嗗劒(y艒u)鍖�锛岄仼鐢ㄤ簬娑堣不闆诲瓙銆佸伐妤�(y猫)鎺у埗銆侀�氫俊绛夐牁鍩�銆�
銆�銆�瑭插櫒浠堕噰鐢� 45nm 宸ヨ棟鍒堕�狅紝鎻愪緵浜嗚睈瀵岀殑閭忚集璩囨簮銆佸祵鍏ュ紡瀛樺劜鍣ㄥ銆佹暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″浠ュ強澶氱ó I/O 妯欐簴鏀寔锛屼娇鍏惰兘澶犻潏娲诲湴婊胯冻鍚勭ó鎳夌敤闇�姹傘��
绯诲垪锛歋partan-6
銆�銆�鍨嬭櫉锛歑C6SLX16-L1CSG324I
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細16,272
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)缃杻瀛�锛岄渶澶栨帴閰嶇疆鑺墖
銆�銆�RAM 绺介噺锛�288 KB
銆�銆�DSP Slice 鏁�(sh霉)閲忥細80
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�236
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�灏佽椤炲瀷锛欳SG (绱伴枔璺濈悆鏌甸櫍鍒�)
銆�銆�寮曡叧鏁�(sh霉)锛�324
XC6SLX16-L1CSG324I 鎻愪緵浜嗛珮搴﹂泦鎴愮殑鍙法绋嬮倧杓硣婧愬拰璞愬瘜鐨勫瑷帴鍙ｅ姛鑳�銆�
銆�銆�1. 閭忚集璩囨簮璞愬瘜锛氬寘鍚秴閬� 16,000 鍊嬮倧杓柈鍏�锛屽彲浠ュ鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)瀛楅浕璺ō瑷�銆�
銆�銆�2. 鍏�(n猫i)缃瓨鍎插櫒锛氭搧鏈� 288 KB 鐨勫鐙� RAM锛屽彲鐢ㄤ簬鏁�(sh霉)鎿�(j霉)绶╁瓨鎴栨煡鎵捐〃绛夊姛鑳�銆�
銆�銆�3. DSP 鏀寔锛氭彁渚� 80 鍊� DSP Slice锛岄仼鍚堢敤浜庨珮鎬ц兘瑷堢畻浠诲嫏濡傛烤娉�銆丗FT 鍜岀煩闄ｉ亱绠楃瓑銆�
銆�銆�4. 澶氱ó I/O 妯欐簴鍏煎锛氭敮鎸� LVCMOS銆丩VDS銆丼STL 绛夊父瑕� I/O 妯欐簴锛屼究浜庤垏涓嶅悓椤炲瀷鐨勫閮ㄨō鍌欓�ｆ帴銆�
銆�銆�5. 浣庡姛鑰楄ō瑷堬細閫氶亷 PowerLite 鎶�琛撻’钁楅檷浣庨潨鎱�(t脿i)鍜屽嫊鎱�(t脿i)鍔熻��锛岀壒鍒ラ仼鍚堜究鏀滃紡瑷倷鍜屽叾浠栧皪鍔熻�楁晱鎰熺殑鎳夌敤鍫存櫙銆�
銆�銆�6. 鍙摯灞曟�у挤锛氭敮鎸佸垎甯冨紡鏅傞悩缍�(w菐ng)绲″拰鍏ㄥ眬鏅傞悩绶╂矕鍗�(q奴)锛屾湁鍔╀簬妲嬪缓寰╅洔鏅傚簭瑷▓銆�
銆�銆�7. 楂樺彲闈犳�э細鍏峰倷鍏�(n猫i)寤鸿嚜妾� (BIST) 鍔熻兘鍜岄尟瑾ゆ娓鍒�锛岀⒑淇濈郴绲�(t菕ng)閬嬭绌�(w臎n)瀹氬彲闈犮��
XC6SLX16-L1CSG324I 寤ｆ硾鎳夌敤浜庨渶瑕侀珮鎬ц兘銆佷綆鍔熻�楀拰浣庢垚鏈В姹烘柟妗堢殑闋樺煙锛�
銆�銆�1. 娑堣不椤為浕瀛愮敘(ch菐n)鍝侊細渚嬪楂樻竻闆昏銆佹闋傜洅銆佹暩(sh霉)纰肩浉姗熺瓑銆�
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栵細鍖呮嫭閬嬪嫊鎺у埗銆佹暩(sh霉)鎿�(j霉)閲囬泦鍜岀洠(ji膩n)鎺х郴绲�(t菕ng)銆�
銆�銆�3. 閫氫俊瑷倷锛氶仼鐢ㄤ簬灏忓瀷鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙浠ュ強鍏朵粬閫氫俊鍩虹瑷柦銆�
銆�銆�4. 閱�(y墨)鐧傝ō鍌欙細濡傝秴鑱叉垚鍍忓剙銆佸績闆诲湒鍎�绛�銆�
銆�銆�5. 姹借粖闆诲瓙锛氱敤浜庝俊鎭妯傜郴绲�(t菕ng)銆侀椐涜紨鍔╃郴绲�(t菕ng)绛�銆�
銆�銆�6. 宓屽叆寮忚瑕猴細鏀寔鍦栧儚铏曠悊绠楁硶鍔犻�熷拰鍌虫劅鍣ㄦ帴鍙ｆ暣鍚�銆�
銆�銆�鐢变簬鍏堕潏娲绘�у拰寮峰ぇ鐨勬�ц兘锛岄�欐 FPGA 閭勫彲浠ョ敤浜庨枊鐧�(f膩)鍘熷瀷椹楄瓑骞宠嚭鎴栧畾鍒� ASIC 瑙ｆ焙鏂规銆�
XC6SLX9-CSG324C, XC6SLX25-CSG324C, XC6SLX45-CSG324C
