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XC6SLX150-2FG676I 鏄� Xilinx 鍏徃 Spartan-6 绯诲垪 FPGA 鐨勪竴鍊嬪瀷铏熴�係partan-6 绯诲垪 FPGA 浠ュ叾楂樻�у児姣斿拰浣庡姛鑰楃壒鎬ц憲绋�锛岄仼鐢ㄤ簬澶氱ó宓屽叆寮忚檿鐞嗗拰閭忚集鎺у埗鎳夌敤銆俋C6SLX150 鏄┎绯诲垪涓殑涓�娆鹃珮鎬ц兘鍣ㄤ欢锛岄噰鐢� 40nm 宸ヨ棟鍒堕��锛屽叿鏈夎睈瀵岀殑閭忚集璩囨簮銆佸瀛樺劜鍣ㄥ拰 DSP Slice锛屽悓鏅傛敮鎸佸绋厤缃伕闋呭拰灏佽褰㈠紡銆傛鍨嬭櫉鐨� -2 琛ㄧず閫熷害绛夌礆鐐� -2锛孎(xi脿n)G676 琛ㄧず灏佽椤炲瀷鐐� Fine Pitch BGA 灏佽锛孖 琛ㄧず宸ユキ(y猫)婧害鑼冨湇锛�-40掳C 鑷� +100掳C锛�銆�
銆�銆�瑭� FPGA 鍣ㄤ欢鐗瑰垾閬╁悎闇�瑕佸ぇ閲忛倧杓硣婧愬拰寰╅洔鍔熻兘鐨勬噳鐢ㄥ牬鏅�锛屼緥濡傞�氫俊绯荤当(t菕ng)銆佽闋诲湒鍍忚檿鐞�銆佸伐妤�(y猫)鑷嫊鍖栨帶鍒朵互鍙婇啱(y墨)鐧傝ō鍌欑瓑銆�
鍣ㄤ欢绯诲垪锛歋partan-6
銆�銆�鍨嬭櫉锛歑C6SLX150
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�灏佽椤炲瀷锛欶G676
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 153,600 鍊� CLB 鏌ユ壘琛� (LUT)
銆�銆�瀛樺劜鍣ㄨ硣婧愶細绱� 2.9 Mb 濉� RAM
銆�銆�DSP Slice 鏁�(sh霉)閲忥細360 鍊�
銆�銆�鐢ㄦ埗 I/O 鏁�(sh霉)閲忥細414 鍊�
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster/Slave SPI銆丅PI 鍜� PROM
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹� 1.2V锛岃紨鍔╅浕澹� 3.3V/2.5V/1.8V
1. XC6SLX150-2FG676I 鎻愪緵浜嗛珮搴﹂潏娲荤殑鍙法绋嬮倧杓灦妲�锛屽厑瑷辫ō瑷堜汉鍝″鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗗拰瀹氬埗鍖栨帴鍙�銆�
銆�銆�2. 鍏х疆鐨� Block RAM 鍜屽垎甯冨紡 RAM 璩囨簮鍙互鐢ㄤ簬瀵︾従(xi脿n) FIFO銆佺珐瀛樹互鍙婂叾浠栧瓨鍎茬祼妲嬨��
銆�銆�3. 闆嗘垚鐨� DSP Slices 鏀寔楂樻晥鐨勪箻娉曠疮鍔犻亱绠�锛岄潪甯搁仼鍚堟烤娉㈠櫒鍜屽叾浠栨暩(sh霉)瀛稿瘑闆嗗瀷绠楁硶銆�
銆�銆�4. 鎻愪緵澶氱ó閰嶇疆閬搁爡锛屽寘鎷潪鏄撳け鎬� Flash 閰嶇疆鑺墖鎴栧閮� PROM 閰嶇疆鑺墖銆�
銆�銆�5. 鏀寔楂橀�熷樊鍒� I/O 妯欐簴锛堝 LVDS 鍜� Mini-LVDS锛�锛屼互婊胯冻楂樻�ц兘閫氫俊闇�姹傘��
銆�銆�6. 鍏х疆 DCM锛堟暩(sh霉)瀛楁檪閻樼鐞嗘ā濉婏級鍜� PLL锛堥帠鐩哥挵(hu谩n)锛�锛屼究浜庢檪閻樼敓鎴愬拰鍚屾銆�
銆�銆�7. FG676 灏佽鎻愪緵楂樺紩鑵虫暩(sh霉)鍜岃壇濂界殑鏁ｇ啽鎬ц兘锛岄仼鍚堝京闆滈浕璺ō瑷�銆�
銆�銆�8. 宸ユキ(y猫)绱氬伐浣滄韩搴﹁寖鍦嶇⒑淇濆湪鎯″姡鐠�(hu谩n)澧冧笅浠嶈兘绌�(w臎n)瀹氶亱琛屻��
1. 閫氫俊绯荤当(t菕ng)锛氬熀甯惰檿鐞�銆佸崝(xi茅)璀拌綁鎻�銆佹暩(sh霉)鎿�(j霉)鍖呰檿鐞嗐��
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細瀵︽檪鍦栧儚澧炲挤銆佹牸寮忚綁鎻涖�佽闋荤法纰艰В纰�銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細閬嬪嫊鎺у埗銆佹鍣ㄤ汉鎶�琛�銆佸偝鎰熷櫒铻嶅悎銆�
銆�銆�4. 閱�(y墨)鐧傝ō鍌欙細瓒呰伈娉㈡垚鍍�銆佺梾浜虹洠(ji膩n)璀风郴绲�(t菕ng)銆佹暩(sh霉)鎿�(j霉)閲囬泦銆�
銆�銆�5. 姹借粖闆诲瓙锛欰DAS 杓斿姪椐曢銆佽粖杓変俊鎭妯傜郴绲�(t菕ng)銆�
銆�銆�6. 娓│鑸囨脯閲忥細鏁�(sh霉)鎿�(j霉)瑷橀寗鍎�銆佷俊铏熺櫦(f膩)鐢熷櫒銆佺ず娉㈠櫒鍓嶇銆�
銆�銆�7. 瀹夐槻鐩�(ji膩n)鎺э細瑕栭牷鍒嗘瀽銆佹櫤鑳界洠(ji膩n)鎺х郴绲�(t菕ng)銆�
XC6SLX150-3FG676I
銆�銆�XC6SLX150T-2FGG676I
銆�銆�XC6SLX150T-3FGG676I
