鏅傞枔锛�2025/5/15 14:31:52
闁辫畝锛�20
XC5VSX50T-2FF665I鏄疿ilinx鍏徃鎺ㄥ嚭鐨刅irtex-5绯诲垪FPGA鍣ㄤ欢涓殑涓�鍊嬪瀷铏熴�傝┎绯诲垪鍩轰簬鍏堥�茬殑65nm宸ヨ棟鍒堕��锛岄泦鎴愪簡澶ч噺鐨勯倧杓柈鍏�銆佸祵鍏ュ紡瀛樺劜鍣ㄥ浠ュ強鏁稿瓧淇¤櫉铏曠悊锛圖SP锛夋ā濉�锛岄仼鐢ㄤ簬楂樻�ц兘瑷堢畻銆侀�氫俊绯荤当銆佸湒鍍忚檿鐞嗗拰宸ユキ(y猫)鑷嫊鍖栫瓑寰╅洔鎳夌敤銆�
銆�銆�Virtex-5绯诲垪涓昏鍒嗙偤澶氬�嬪瓙绯诲垪锛屽叾涓璖X绯诲垪灏堟敞浜庨珮鎬ц兘鐨勬暩瀛椾俊铏熻檿鐞嗗姛鑳姐�俋C5VSX50T浣滅偤SX瀛愮郴鍒楃殑涓�鍝�锛屾搧鏈夊挤澶х殑DSP Slice璩囨簮锛岃兘澶犳豢瓒冲京闆滅殑绠楁硶闇�姹傘�傛澶�锛屽叾璞愬瘜鐨勫瑷帴鍙ｅ拰闈堟椿鐨勯厤缃伕闋咃紝浣垮叾鎴愮偤鐪惧楂樼鎳夌敤鐨勭悊鎯抽伕鎿�銆�
鍨嬭櫉锛歑C5VSX50T-2FF665I
銆�銆�绯诲垪锛歏irtex-5 SX
銆�銆�宸ヨ棟鍒剁▼锛�65nm
銆�銆�閰嶇疆妯″紡锛歁aster Serial, Slave Serial, Slave Parallel, Boundary Scan
銆�銆�I/O寮曡叧鏁革細665
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 70掳C锛�锛屽伐妤�(y猫)绱氾紙-40掳C 鑷� 100掳C锛�
銆�銆�灏佽褰㈠紡锛欶FG665
銆�銆�鍏ч儴璩囨簮锛氱磩50,000鍊嬮倧杓柈鍏�
銆�銆�DSP Slice鏁搁噺锛�320鍊�
銆�銆�Block RAM澶�?銆傛澀s3.7MB
銆�銆�閰嶇疆Flash锛氫笉闆嗘垚锛堥渶澶栨帴锛�
XC5VSX50T-2FF665I鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘DSP Slice锛氭瘡鍊婦SP Slice鍖呭惈18x25浣嶄箻娉曞櫒鍙�48浣嶅姞/娓涙硶鍣�锛屾敮鎸侀珮鏁堢殑瀹氶粸鎴栨诞榛為亱绠�锛岄仼鍚堥煶闋�銆佽闋讳互鍙婂叾浠栨暩鎿氬瘑闆嗗瀷鎳夌敤銆�
銆�銆�2. 澶у閲忓祵鍏ュ紡瀛樺劜鍣細鎻愪緵澶氶仈鏁哥櫨Kb鐨勫垎甯冨紡RAM鍜岀磩3.7MB鐨凚lock RAM锛屽彲瀵︾従寰╅洔鐨勭珐瀛樿ō瑷堛��
銆�銆�3. 鍙法绋嬫檪閻樼鐞嗭細鍏х疆Differential Clock Management (DCM) 妯″锛屾敮鎸佸璺几鍏ユ檪閻樺垎闋汇�佸�嶉牷浠ュ強鐩哥Щ鎺у埗銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細閮ㄥ垎Virtex-5鍣ㄤ欢閭勬敮鎸侀珮閬�6.5Gbps鐨勯珮閫熶覆琛屾敹鐧�(f膩)鍔熻兘锛堝叿楂斿彇姹轰簬瀛愮郴鍒楋級銆�
銆�銆�5. 闈堟椿鐨勯浕婧愮鐞嗭細閲囩敤澶氶浕澹撹粚瑷▓锛屽厑瑷辩敤鎴舵牴鎿氬闅涢渶姹傚劒(y艒u)鍖栧姛鑰楄垏鎬ц兘涔嬮枔鐨勫钩琛°��
銆�銆�6. 鏀寔澶氱ó閰嶇疆妯″紡锛氬彲浠ラ�氶亷JTAG銆丼electMAP銆丼lave Serial绛夋柟寮忓姞杓夐厤缃枃浠讹紝渚夸簬涓嶅悓鍫存櫙涓嬬殑浣跨敤銆�
銆�銆�7. 寤ｆ硾鐨処/O妯欐簴鍏煎鎬э細鏀寔LVCMOS銆丩VDS銆丠STL绛夊绋浕骞虫婧栵紝閬╂噳涓嶅悓鐨勫閮ㄨō鍌欓�ｆ帴闇�姹�銆�
瑭茶姱鐗囧唬娉涙噳鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 閫氫俊鍩虹瑷柦锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙涓殑鏁告摎鍖呰檿鐞嗗拰鍗旇杞夋彌銆�
銆�銆�2. 鍦栧儚鑸囪闋昏檿鐞嗭細鐢ㄤ簬瀵︽檪鍦栧儚閲囬泦銆佸绺法纰煎強澧炲挤绛夊姛鑳�銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細鍦ㄩ亱鍕曟帶鍒�銆佹鍣ㄨ瑕虹瓑闋樺煙鐧�(f膩)鎻噸瑕佷綔鐢�銆�
銆�銆�4. 閱�(y墨)鐧傛垚鍍忚ō鍌欙細鏀寔瓒呰伈娉�銆丆T鎺冩弿绛夐珮绮惧害褰卞儚鐢熸垚銆�
銆�銆�5. 娓│娓噺鍎�鍣細鐐虹ず娉㈠櫒銆佷俊铏熸簮绛夌敘鍝佹彁渚涙牳蹇冭▓绠楄兘鍔涖��
銆�銆�6. 鑸┖鑸ぉ鍜屽湅闃诧細鎳夌敤浜庨浄閬旂郴绲便�佽(w猫i)鏄熼�氫俊绛夊皪鍙潬鎬ц姹傛サ楂樼殑鍫村悎銆�
XC5VSX50T-3FF665C, XC5VLX50T-2FF665C
