灏佽�濓細FFG665
銆�銆�閫熷害绛夌礆(j铆)锛�-1
銆�銆�閰嶇疆闁冨瓨锛氫笉鍏�(n猫i)缃�
銆�銆�鍏�(n猫i)鏍搁浕澹擄細1.0V
銆�銆�I/O闆诲�擄��1.8V, 2.5V, 3.3V
銆�銆�FPGA绯诲垪锛歏irtex-5 SX
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱�5钀�(w脿n)
銆�銆�DSP Slice鏁�(sh霉)閲忥細420鍊�(g猫)
銆�銆�RAM瀹归噺锛�2700 Kb
銆�銆�鏈�澶х敤鎴�(h霉)I/O鏁�(sh霉)锛�484
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master SelectMAP, Slave BPI

XC5VSX50T-1FF665C閲囩敤65nm CMOS宸ヨ棟鍒堕��锛屽叿鏈夊嚭鑹茬殑鎬ц兘鍔熻�楁瘮銆�
銆�銆�瑭茶姱鐗囧叿鍌欏挤(qi谩ng)澶х殑淇¤櫉(h脿o)铏曠悊鑳藉姏锛屾搧鏈�420鍊�(g猫)DSP Slice锛屾瘡鍊�(g猫)Slice鍏�(n猫i)閮ㄩ泦鎴愪簡灏�(zhu膩n)鐢ㄤ箻娉曞櫒鍜屽姞娉曞櫒锛屽彲浠ラ’钁楀姞閫熸暩(sh霉)鍊艰▓(j矛)绠椾换鍕�(w霉)銆�
銆�銆�鑺�鐗囧寘鍚�澶ч噺宓屽叆寮忓�婂瓨鍎�(ch菙)鍣�锛圔lock RAM锛�锛岀附?c猫)钀樼獰_(d谩)鍒�2700 Kb锛岄仼鍚堢珐瀛樻暩(sh霉)鎿�(j霉)鎴�?q奴)宕縁(xi脿n)FIFO绛夊姛鑳�銆�
銆�銆�Virtex-5绯诲垪鏀�鎸佸�氱ó閰嶇疆妯″紡锛屽厑瑷遍�氶亷(gu貌)澶栭儴闁冨瓨鎴栭厤缃�瑷�(sh猫)鍌欏姞杓夋瘮鐗规祦銆�
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XC5VSX50T-1FFG665C, XC5VSX50T-2FF665C, XC5VSX50T-3FF665C