XC5VLX85-2FFG676C 鏅傞枔锛�2023/7/18 17:52:29 闁辫畝锛�771

鎻忚堪

銆€銆€XC5VLX85-2FFG676C鎻愪緵浜咶PGA甯傚牬涓婃渶鏂版渶寮峰ぇ鐨勫姛鑳�銆俈irtex-5绯诲垪浣跨敤绗簩浠SMBL锛堥珮绱氱妯″妯″锛夊熀浜庡垪鐨勬灦妲�(g貌u)锛屽寘鍚簲鍊嬩笉鍚岀殑骞宠嚭锛堝瓙绯诲垪锛�锛屾槸鎵€鏈塅PGA绯诲垪鎻愪緵鐨勬渶澶氶伕鎿�銆傛瘡鍊嬪钩鑷洪兘鍖呭惈涓嶅悓姣斾緥鐨勫姛鑳�锛屼互婊胯冻鍚勭ó楂樼礆閭忚集瑷�(sh猫)瑷堢殑闇€姹�銆傞櫎浜嗘渶鍏堥€�(j矛n)鐨勯珮鎬ц兘閭忚集绲�(ji茅)妲�(g貌u)澶栵紝Virtex-5FPGA閭勫寘鍚 ū澶氱‖鏍窱P绯荤当(t菕ng)绱氭ā濉�锛屽寘鎷挤澶х殑36-Kbit濉奟AM/FIFO銆佺浜屼唬25x18DSPslice銆佸叿鏈夊収(n猫i)缃姛鑳界殑SelectIO鎶€琛�(sh霉)鏁�(sh霉)瀛楁帶鍒堕樆鎶�銆丆hipSync婧愬悓姝ユ帴鍙ｅ銆佺郴绲�(t菕ng)鐩�(ji膩n)瑕栧櫒鍔熻兘銆佸叿鏈夐泦鎴怐CM锛堟暩(sh霉)瀛楁檪閻樼鐞嗗櫒锛夊拰閹栫浉鐠�(hu谩n)(PLL)鏅傞悩鐧�(f膩)鐢熷櫒浠ュ強楂樼礆閰嶇疆閬搁爡鐨勫寮峰瀷鏅傞悩绠＄悊濉娿€傚叾浠栧钩鑷虹浉闂�(gu膩n)鍔熻兘鍖呮嫭鐢ㄤ簬澧炲挤涓茶閫ｆ帴鐨勫姛鐜囧劒(y艒u)鍖栭珮閫熶覆琛屾敹鐧�(f膩)鍣ㄦā濉�銆佺鍚圥CIExpress?鐨勯泦鎴愮榛炴ā濉娿€佷笁妯″紡浠ュお缍�(w菐ng)MAC锛堝獟楂旇í鍟忔帶鍒跺櫒锛夊拰楂樻€ц兘PowerPC?440寰檿鐞嗗櫒宓屽叆寮忔ā濉�銆俋C5VLX85-2FFG676C鐐烘豢瓒抽珮鎬ц兘閭忚集瑷�(sh猫)瑷堜汉鍝�銆侀珮鎬ц兘DSP瑷�(sh猫)瑷堜汉鍝″拰楂樻€ц兘宓屽叆寮忕郴绲�(t菕ng)瑷�(sh猫)瑷堜汉鍝＄殑闇€姹傛彁渚涗簡寰堝ソ鐨勮В姹烘柟妗�銆�

鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�	XC5VLX85-2FFG676C
鎻忚堪	闆嗘垚闆昏矾FPGA 440 I / O 676FCBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	Xilinx鍏徃
绯诲垪	Virtex?-5LX
鎵撳寘	鎵樼洡
闆诲-闆绘簮	0.95V?1.05V
宸ヤ綔婧害	0掳C?85掳C(TJ)
鍖呰/绠�	676-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	676-FCBGA(27x27)
鍩烘湰闆朵欢铏�	XC5VLX85

鐢�(ch菐n)鍝佸湒鐗�

XC5VLX85-2FFG676C

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍒堕€犲晢鍖呰瑾槑	27 X 27 MM锛岀劇閴涳紝F(xi脿n)BGA-676
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	娲绘€�
鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
鏈€澶ф檪閻橀牷鐜�	1265.0鍏嗚但
JESD-30浠ｇ⒓	S-PBGA-B676
JESD-609浠ｇ⒓	e1
CLB鏁�(sh霉)閲�	6480.0
杓稿叆鏁�(sh霉)閲�	440.0
閭忚集鍠厓鏁�(sh霉)	82944.0
杓稿嚭鏁�(sh霉)閲�	440.0
绔瓙鏁�(sh霉)	676
鏈€浣庡伐浣滄韩搴�	0鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
绲勭箶	6480 CLBS
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA676,26X26,40
鍖呰褰㈢媭	鍥涙柟褰�
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
宄板€煎洖娴佹韩搴�(鈩�)	245
闆绘簮	1,2.5
搴ч珮	3.0姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	1.0浼�
鏈€灏忎緵闆婚浕澹�	0.95浼�
鏈€澶ч浕婧愰浕澹�	1.05浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn95.5Ag4.0Cu0.5)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴�-鏈€澶у€�(绉�)	30
闀峰害	27.0姣背
瀵害	27.0姣背

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

灞€�	鎻忚堪
REACH鐙€鎱�(t脿i)	REACH涓嶅彈褰遍熆
RoHS鐙€鎱�(t脿i)	绗﹀悎ROHS3
婵曟埃鏁忔劅搴�(MSL)	4(72灏忔檪)

鐗归粸

浜斿€嬪钩鑷篖X銆丩XT銆丼XT銆乀XT鍜孎XT
璺ㄥ钩鑷哄吋瀹规€�
鏈€鍏堥€�(j矛n)銆侀珮鎬ц兘銆佹渶浣冲埄鐢ㄧ巼銆丗PGA绲�(ji茅)妲�(g貌u)
寮峰ぇ鐨勬檪閻樼鐞嗙璨�(CMT)鏅傞悩
楂樻€ц兘骞惰閬告搰鎶€琛�(sh霉)
36Kbit濉奟AM/FIFO
楂樼礆DSP48E鐗�
鎵€鏈夎ō(sh猫)鍌欎笂鐨勭郴绲�(t菕ng)鐩�(ji膩n)鎺ц兘鍔�
闈堟椿鐨勯厤缃伕闋�
鐢ㄤ簬PCIExpress瑷�(sh猫)瑷堢殑闆嗘垚绔粸濉�
涓夋ā寮�10/100/1000Mb/s浠ュお缍�(w菐ng)MAC
RocketIOGTP鏀剁櫦(f膩)鍣�100Mb/s鑷�3.75Gb/s
PowerPC440寰檿鐞嗗櫒
65绱嶇背閵匔MOS宸ヨ棟鎶€琛�(sh霉)
1.0浼忔牳蹇冮浕澹�

闆昏矾鍦�

CAD妯″瀷

XC5VLX85-2FFG676C绗﹁櫉

XC5VLX85-2FFG676C鑵冲嵃

灏佽

XC5VLX85-2FFG676C灏佽

鏇夸唬鍨嬭櫉

鍨嬭櫉	鍒堕€犲晢	鍝佸悕	鎻忚堪
XC5VLX85-3FFG676C	璩介潏鎬�	FPGA鑺墖	82944Cells 65nm(CMOS) Technology 1V 676Pin FCBGA
XC5VLX85-2FF676I	璩介潏鎬�	FPGA鑺墖	82944Cells 65nm (CMOS) Technology 1V 676Pin FCBGA
XC5VLX85-1FFG676I	璩介潏鎬�	FPGA鑺墖	82944Cells 65nm (CMOS) Technology 1V 676Pin FCBGA