鑺�鐗囩郴鍒楋細Virtex-5
銆�銆�鍨嬭櫉(h脿o)锛歑C5VLX50T-1FFV665I
銆�銆�鍒剁▼宸ヨ棟锛�65nm
銆�銆�FPGA 瀛愮郴鍒楋細LX (Logic Extra)
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 50,000 鍊�(g猫) CLB
銆�銆�Block RAM锛�2.7 Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細320
銆�銆�I/O 鏁�(sh霉)閲忥細496
銆�銆�閰嶇疆妯″紡锛歋electMAP 鍜� Master/Slave SPI
銆�銆�灏佽�濋��(l猫i)鍨嬶細FFG665 (Flip Chip Fine Pitch BGA)
銆�銆�閫熷害绛夌礆(j铆)锛�-1 (鏈�蹇�绱�(j铆)鍒�)
銆�銆�宸ヤ綔闆诲�擄細鍏�(n猫i)鏍� 1.0V锛孖/O 鍙�閰嶇疆鐐� 1.8V/2.5V/3.3V

XC5VLX50T-1FFV665I 鎻愪緵浜嗗嚭鑹茬殑鎬ц兘鑸囬潏娲绘��锛岄仼鐢ㄤ簬寰�(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏�(h脿o)铏曠悊鍜屾帶鍒朵换鍕�(w霉)銆�
銆�銆�1. 楂橀倧杓�瀵嗗害锛氬叿鍌欏ぇ绱� 50,000 鍊�(g猫)鍙�绶ㄧ▼閭忚集鍠�鍏�锛岃兘澶�?q奴)宕縁(xi脿n)寰�(f霉)闆滅殑绠楁硶鍜屽姛鑳芥ā濉娿��
銆�銆�2. 寮�(qi谩ng)澶х殑 DSP 鍔熻兘锛氶泦鎴� 320 鍊�(g猫) DSP Slice锛屾敮鎸侀珮绮惧害涔樻硶绱�鍔犻��(y霉n)绠�锛岄仼鍚堜俊铏�(h脿o)铏曠悊鍜屾暩(sh霉)瀛�(xu茅)瀵嗛泦鍨嬫噳(y墨ng)鐢�銆�
銆�銆�3. 楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛氶洊鐒� LX 绯诲垪鏈�鍖呭惈楂樼��涓茶�屾敹鐧�(f膩)鍣�锛屼絾鍙�浠ラ�氶亷(gu貌)澶栭儴 PHY 鎴� IP 鏍告摯(ku貌)灞曢珮閫熸帴鍙ｅ姛鑳姐��
銆�銆�4. 澶у�归�� Block RAM锛氭彁渚� 2.7Mb 鐨勫祵鍏ュ紡瀛樺劜(ch菙)鍣ㄨ硣婧�锛屾豢(m菐n)瓒虫暩(sh霉)鎿�(j霉)绶╂矕鍜屾煡鎵捐〃鐨勯渶姹�銆�
銆�銆�5. 闈堟椿鐨� I/O 鏀�鎸侊細澶氶��(d谩) 496 鍊�(g猫)鐢ㄦ埗(h霉)鍙�绶ㄧ�� I/O 寮曡叧锛屾敮鎸佸�氱ó闆诲钩妯�(bi膩o)婧�(zh菙n)鍜屾帴鍙ｅ崝(xi茅)璀般��
銆�銆�6. 蹇�閫熷暉鍕�(d貌ng)鏅�(sh铆)闁擄細鏀�鎸佸�氱ó閰嶇疆妯″紡锛堝�� SelectMAP 鍜� SPI锛�锛岀府鐭�绯荤��(t菕ng)鍒濆�嬪寲鏅�(sh铆)闁撱��
銆�銆�7. 浣庡姛鑰楄ō(sh猫)瑷�(j矛)锛氶�氶亷(gu貌)鍕�(d貌ng)鎱�(t脿i)鍔熻�楃�＄悊鍜屾��(sh铆)閻橀杸(m茅n)鎺ф妧琛�(sh霉)闄嶄綆鏁撮珨鑳借��銆�
銆�銆�8. 寤ｆ硾鐨� IP 鏍告敮鎸侊細Xilinx 鎻愪緵澶ч噺鐝�(xi脿n)鎴愮殑 IP 鏍�锛屽寘鎷�浠ュお缍�(w菐ng) MAC銆丳CIe 鎺у埗鍣ㄣ�丗FT 绛夛紝绨�(ji菐n)鍖栭枊(k膩i)鐧�(f膩)娴佺▼銆�

XC5VLX50T-1FFV665I 涓昏�佹��(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊瑷�(sh猫)鍌欙細濡傚熀甯惰檿鐞�銆佷俊閬撶法纰艰В纰笺�佷俊铏�(h脿o)瑾�(di脿o)鍒惰В瑾�(di脿o)绛�銆�
銆�銆�2. 鏁�(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞嗭細渚嬪�傚伐妤�(y猫)鑷�鍕�(d貌ng)鍖栨帶鍒剁郴绲�(t菕ng)涓�鐨勫��(sh铆)鏅�(sh铆)鏁�(sh霉)鎿�(j霉)铏曠悊妯″�娿��
銆�銆�3. 鍦栧儚铏曠悊锛氱敤浜庨啱(y墨)鐧傚奖鍍�銆佹��(j墨)鍣ㄨ�栬��(ju茅)鎴栬�栭牷鐩�(ji膩n)鎺х郴绲�(t菕ng)鐨勫湒鍍忓�炲��(qi谩ng)銆佸�撶府鍜屽偝杓�銆�
銆�銆�4. 娓�(c猫)瑭︽脯(c猫)閲忥細妲�(g貌u)寤洪珮鎬ц兘娓�(c猫)瑭﹀剙鍣�锛屽�傜ず娉㈠櫒銆佷俊铏�(h脿o)鐧�(f膩)鐢熷櫒绛�銆�
銆�銆�5. 宓屽叆寮忕郴绲�(t菕ng)锛氫綔鐐轰富鎺ц姱鐗�锛岀�＄悊寰�(f霉)闆滅郴绲�(t菕ng)涓�鐨勫�氬��(g猫)澶栬ō(sh猫)鍜屼换鍕�(w霉)銆�
銆�銆�6. 杌嶄簨鑸囪埅澶╋細鐢变簬鍏堕珮鎬ц兘鍜屽彲闈犳��锛屽彲鐢ㄤ簬闆烽仈(d谩)绯荤当(t菕ng)銆佽��(w猫i)鏄熼�氫俊鍜屽皫(d菐o)鑸�瑷�(sh猫)鍌欍��
銆�銆�7. 楂樻�ц兘瑷�(j矛)绠楋細鍩�(zh铆)琛屽苟琛岃▓(j矛)绠椾换鍕�(w霉)锛屽�傜�戝��(xu茅)浠跨湡銆佸瘑纰肩牬瑙ｇ瓑銆�

XC5VLX50T-1FFG665C
銆�銆�XC5VLX50T-1FFG665I
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