鏅傞枔锛�2025/4/30 11:12:35
闁辫畝锛�34
XC5VLX50-3FFG324I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-5 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪叿楂斿瀷铏�銆俈irtex-5 绯诲垪鏄熀浜� 65nm 宸ヨ棟鎶�琛撳埗閫犵殑楂樻�ц兘鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛岄仼鐢ㄤ簬閫氫俊銆佷俊铏熻檿鐞�銆佸湒鍍忚檿鐞嗐�佸祵鍏ュ紡绯荤当(t菕ng)浠ュ強鍚勭ó寰╅洔閭忚集瑷▓绛夋噳鐢ㄩ牁鍩�銆�
銆�銆�瑭茬郴鍒� FPGA 鎻愪緵浜嗚睈瀵岀殑璩囨簮鍜岄潏娲荤殑鏋舵(g貌u)锛屾敮鎸佸绋珮绱氱壒鎬у DSP Slice銆丅lock RAM 鍜屽垎甯冨紡 RAM锛屽苟涓旈泦鎴愪簡楂橀�熶覆琛屾敹鐧�(f膩)鍣ㄧ瓑鍔熻兘妯″锛屼娇鍏惰兘澶犳豢瓒崇従(xi脿n)浠ｉ浕瀛愮郴绲�(t菕ng)灏嶆�ц兘鍜屽姛鑳界殑闇�姹�銆�
鍣ㄤ欢椤炲瀷锛欶PGA
銆�銆�宸ヨ棟鍒剁▼锛�65nm
銆�銆�鍏�(n猫i)鏍搁浕澹擄細1.0V
銆�銆�I/O 闆诲锛�1.8V/2.5V/3.3V
銆�銆�灏佽褰㈠紡锛欶FG324
銆�銆�閫熷害绛夌礆锛�-3
銆�銆�閰嶇疆妯″紡锛氬緸灞�(Slave)鎴栦富鎺�(Master)
銆�銆�瀛樺劜鍠厓锛氶珮閬� 9MB Block RAM
銆�銆�DSP Slice 鏁�(sh霉)閲忥細576
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 50K
銆�銆�涓茶鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂橀仈 6.5Gbps
XC5VLX50-3FFG324I 鎻愪緵浜嗗挤澶х殑閭忚集璩囨簮鍜岄珮鎬ц兘鐨勬灦妲�(g貌u)锛�
銆�銆�1. 鏀寔澶氶仈 50K 鐨勯倧杓柈鍏冿紝鍙互瀵︾従(xi脿n)寰╅洔鐨勬暩(sh霉)瀛楅浕璺ō瑷�銆�
銆�銆�2. 闆嗘垚浜� 576 鍊� DSP Slice锛岄潪甯搁仼鍚堢敤浜庨珮鎬ц兘鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�銆�
銆�銆�3. 鍖呭惈澶氶仈 9MB 鐨� Block RAM锛屽彲鐢ㄤ簬鏁�(sh霉)鎿�(j霉)绶╂矕銆佹煡鎵捐〃绛夊姛鑳�銆�
銆�銆�4. 鍏�(n猫i)缃珮閫熶覆琛屾敹鐧�(f膩)鍣�锛屾渶楂樻敮鎸� 6.5Gbps 鏁�(sh霉)鎿�(j霉)鍌宠几閫熺巼锛岄仼鍚堝厜绾栭�氫俊绛夐珮甯跺鎳夌敤鍫存櫙銆�
銆�銆�5. 鏀寔澶氱ó閰嶇疆妯″紡锛圫lave 鎴� Master锛�锛屼究浜庣敤鎴舵牴鎿�(j霉)瀵﹂殯闇�姹傞伕鎿囧悎閬╃殑鏂瑰紡鍔犺級绋嬪簭銆�
銆�銆�6. 鎻愪緵闈堟椿鐨� I/O 妯欐簴鏀寔锛屽吋瀹瑰绋笉鍚岀殑鎺ュ彛鍗�(xi茅)璀�銆�
銆�銆�7. 閲囩敤 65nm 鍒堕�犲伐钘�锛屽湪闄嶄綆鍔熻�楃殑鍚屾檪鎻愰珮浜嗚姱鐗囩殑鏁撮珨鎬ц兘銆�
XC5VLX50-3FFG324I 寤ｆ硾鎳夌敤浜庡鍊嬭妤�(y猫)鍜岄牁鍩燂細
銆�銆�1. 閫氫俊瑷倷锛氬璺敱鍣�銆佷氦鎻涙銆佸熀绔欑瓑锛岀敤浜庢暩(sh霉)鎿�(j霉)鍖呰檿鐞嗐�佸崝(xi茅)璀拌綁(zhu菐n)鎻涚瓑浠诲嫏銆�
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鐢ㄤ簬瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮�銆佸鏅傚湒鍍忓垎鏋愮瓑闋樺煙銆�
銆�銆�3. 宓屽叆寮忕郴绲�(t菕ng)锛氫綔鐐烘牳蹇冭檿鐞嗗櫒浣跨敤锛屾(g貌u)寤哄畾鍒跺寲鐨勫祵鍏ュ紡瑷堢畻骞宠嚭銆�
銆�銆�4. 娓│娓噺鍎�鍣細鐢ㄤ簬淇¤櫉鐢熸垚銆侀噰闆嗗拰鍒嗘瀽绛夊姛鑳�銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忚ō鍌欙細渚嬪瓒呰伈娉㈣ê鏂峰剙銆丆T 鎺冩弿鍎�涓渶瑕侀�茶澶ч噺骞惰閬嬬畻鐨勯儴鍒�銆�
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栨帶鍒讹細璨犺铂寰╅洔鐨勫鏅傛帶鍒剁畻娉曞煼(zh铆)琛屻��
XC5VLX50T-3FFG324I
銆�銆�XC5VLX50-3FFG676I
銆�銆�XC5VLX50T-3FFG676I
